Mesa (staging/21.2): isl: only bump the min row pitch for display when not specified

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Module: Mesa
Branch: staging/21.2
Commit: 7c088e7024eb87d79b43e6da8ca6e1639664e520
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c088e7024eb87d79b43e6da8ca6e1639664e520

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Fri Sep 24 13:28:05 2021 +0300

isl: only bump the min row pitch for display when not specified

If the ISL caller didn't specify a row_pitch_B, let's use the
NVIDIA/AMD requirements. Otherwise keep using the Intel requirement,
as the caller is likely trying to import a buffer and if we can deal
with that row_pitch_B, we should accept it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: a3a4517f4147a0 ("isl: Work around NVIDIA and AMD display pitch requirements")
Reported-by: Dongwon Kim <dongwon.kim at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13024>
(cherry picked from commit 9fb2c84768c30702fd8177b81ec0bb45c110bdd7)

---

 .pick_status.json   |  2 +-
 src/intel/isl/isl.c | 16 +++++++++++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index a4ebe86f0de..4a4af598da9 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -337,7 +337,7 @@
         "description": "isl: only bump the min row pitch for display when not specified",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "a3a4517f4147a0a7c1b34a4bcd42de45d552df5f"
     },
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 0ab9937a2c8..0cc2c3ef007 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1479,10 +1479,20 @@ isl_calc_row_pitch_alignment(const struct isl_device *dev,
     *    "When using linear memory, this must be at least 64 byte aligned."
     *
     * However, when displaying on NVIDIA and recent AMD GPUs via PRIME,
-    * we need a larger pitch of 256 bytes.  We do that just in case.
+    * we need a larger pitch of 256 bytes.
+    *
+    * If the ISL caller didn't specify a row_pitch_B, then we should assume
+    * the NVIDIA/AMD requirements. Otherwise, if we have a specified
+    * row_pitch_B, this is probably because the caller is trying to import a
+    * buffer. In that case we limit the minimum row pitch to the Intel HW
+    * requirement.
     */
-   if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT)
-      alignment = isl_align(alignment, 256);
+   if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
+      if (surf_info->row_pitch_B == 0)
+         alignment = isl_align(alignment, 256);
+      else
+         alignment = isl_align(alignment, 64);
+   }
 
    return alignment;
 }