Mesa (main): freedreno/ir3+isa: Cleanup bindless cat5 samp/tex encoding

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 9516d8ce98b40a93b70d8c68d57bf2a2ccdd1ece
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9516d8ce98b40a93b70d8c68d57bf2a2ccdd1ece

Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Oct 12 10:57:24 2021 -0700

freedreno/ir3+isa: Cleanup bindless cat5 samp/tex encoding

Don't let the way they are encoded at the isa level leak thru to the
ir3 level.

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

---

 src/freedreno/ir3/ir3_compiler_nir.c |  9 +++------
 src/freedreno/ir3/ir3_parser.y       |  2 +-
 src/freedreno/ir3/ir3_print.c        | 10 ++--------
 src/freedreno/isa/ir3-cat5.xml       |  7 +------
 4 files changed, 7 insertions(+), 21 deletions(-)

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 540d7b606c6..420e5b40837 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1117,7 +1117,7 @@ struct tex_src_info {
    /* For prefetch */
    unsigned tex_base, samp_base, tex_idx, samp_idx;
    /* For normal tex instructions */
-   unsigned base, combined_idx, a1_val, flags;
+   unsigned base, a1_val, flags;
    struct ir3_instruction *samp_tex;
 };
 
@@ -1150,11 +1150,9 @@ get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
          if (info.tex_idx < 16) {
             /* Everything fits within the instruction */
             info.base = info.tex_base;
-            info.combined_idx = info.samp_idx | (info.tex_idx << 4);
          } else {
             info.base = info.tex_base;
             info.a1_val = info.tex_idx << 3;
-            info.combined_idx = 0;
             info.flags |= IR3_INSTR_A1EN;
          }
          info.samp_tex = NULL;
@@ -1200,7 +1198,8 @@ emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
    }
    if (info.flags & IR3_INSTR_B) {
       sam->cat5.tex_base = info.base;
-      sam->cat5.samp = info.combined_idx;
+      sam->cat5.samp = info.samp_idx;
+      sam->cat5.tex  = info.tex_idx;
    }
    return sam;
 }
@@ -2305,11 +2304,9 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
               info.tex_base == info.samp_base)) {
             /* Everything fits within the instruction */
             info.base = info.tex_base;
-            info.combined_idx = info.samp_idx | (info.tex_idx << 4);
          } else {
             info.base = info.tex_base;
             info.a1_val = info.tex_idx << 3 | info.samp_base;
-            info.combined_idx = info.samp_idx;
             info.flags |= IR3_INSTR_A1EN;
          }
          info.samp_tex = NULL;
diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y
index 3be8fa0426b..63f1cccd946 100644
--- a/src/freedreno/ir3/ir3_parser.y
+++ b/src/freedreno/ir3/ir3_parser.y
@@ -984,7 +984,7 @@ cat5_flags:
 |                  cat5_flag cat5_flags
 
 cat5_samp:         T_SAMP         { instr->cat5.samp = $1; }
-cat5_tex:          T_TEX          { if (instr->flags & IR3_INSTR_B) instr->cat5.samp |= ($1 << 4); else instr->cat5.tex = $1; }
+cat5_tex:          T_TEX          { instr->cat5.tex = $1; }
 cat5_type:         '(' type ')'   { instr->cat5.type = $2; }
 cat5_a1:           src_reg        { instr->flags |= IR3_INSTR_A1EN; }
 
diff --git a/src/freedreno/ir3/ir3_print.c b/src/freedreno/ir3/ir3_print.c
index 423097525fc..dd57bdc6853 100644
--- a/src/freedreno/ir3/ir3_print.c
+++ b/src/freedreno/ir3/ir3_print.c
@@ -340,14 +340,8 @@ print_instr(struct log_stream *stream, struct ir3_instruction *instr, int lvl)
    }
 
    if (is_tex(instr) && !(instr->flags & IR3_INSTR_S2EN)) {
-      if (!!(instr->flags & IR3_INSTR_B)) {
-         if (!!(instr->flags & IR3_INSTR_A1EN)) {
-            mesa_log_stream_printf(stream, ", s#%d", instr->cat5.samp);
-         } else {
-            mesa_log_stream_printf(stream, ", s#%d, t#%d",
-                                   instr->cat5.samp & 0xf,
-                                   instr->cat5.samp >> 4);
-         }
+      if (!!(instr->flags & IR3_INSTR_B) && !!(instr->flags & IR3_INSTR_A1EN)) {
+         mesa_log_stream_printf(stream, ", s#%d", instr->cat5.samp);
       } else {
          mesa_log_stream_printf(stream, ", s#%d, t#%d", instr->cat5.samp,
                                 instr->cat5.tex);
diff --git a/src/freedreno/isa/ir3-cat5.xml b/src/freedreno/isa/ir3-cat5.xml
index a75c428d697..38fa5b77c40 100644
--- a/src/freedreno/isa/ir3-cat5.xml
+++ b/src/freedreno/isa/ir3-cat5.xml
@@ -481,12 +481,7 @@ SOFTWARE.
 	<display/>
 	<assert low="0" high="3">0000</assert>
 	<encode type="struct ir3_instruction *">
-		<!--
-			TODO properly decouple the encoding from ir3 IR in this
-			case.. the IR has no business knowing how this gets
-			encoded into "SRC3"..
-		 -->
-		<map name="TEX">src->cat5.samp >> 4</map>
+		<map name="TEX">src->cat5.tex</map>
 	</encode>
 </bitset>