Mesa (main): isaspec: Fix derived field width

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Module: Mesa
Branch: main
Commit: e01759e6f31b958c152ed42b2fc9cfe4eddfe31e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e01759e6f31b958c152ed42b2fc9cfe4eddfe31e

Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Oct 12 14:22:25 2021 -0700

isaspec: Fix derived field width

The low/high bit positions should be integers.

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

---

 src/compiler/isaspec/isa.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/isaspec/isa.py b/src/compiler/isaspec/isa.py
index 22b8991d4c9..acf5f841cfd 100644
--- a/src/compiler/isaspec/isa.py
+++ b/src/compiler/isaspec/isa.py
@@ -165,7 +165,7 @@ class BitSetDerivedField(BitSetField):
         # where sign extension is needed.  We just repurpose the 'high'
         # field for that to make '1 + high - low' work out
         if 'width' in xml.attrib:
-            self.high = xml.attrib['width'] + ' - 1'
+            self.high = int(xml.attrib['width']) - 1
         self.name = xml.attrib['name']
         self.type = xml.attrib['type']
         if 'expr' in xml.attrib: