Mesa (main): intel/compiler: Rename vec4 test fixtures
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Fri Oct 15 17:45:50 UTC 2021
Module: Mesa
Branch: main
Commit: 35b69907061324c8432664b24ea8319c31e65564
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=35b69907061324c8432664b24ea8319c31e65564
Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date: Mon Oct 11 23:20:39 2021 -0700
intel/compiler: Rename vec4 test fixtures
Include vec4 in their names to avoid same names as the fs
counterparts. This will allow compiling all the tests together in the
future.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13303>
---
src/intel/compiler/test_vec4_cmod_propagation.cpp | 52 +++++++++++-----------
src/intel/compiler/test_vec4_copy_propagation.cpp | 10 ++---
.../compiler/test_vec4_dead_code_eliminate.cpp | 8 ++--
src/intel/compiler/test_vec4_register_coalesce.cpp | 16 +++----
4 files changed, 43 insertions(+), 43 deletions(-)
diff --git a/src/intel/compiler/test_vec4_cmod_propagation.cpp b/src/intel/compiler/test_vec4_cmod_propagation.cpp
index 21cee5d64ac..0d237477ce4 100644
--- a/src/intel/compiler/test_vec4_cmod_propagation.cpp
+++ b/src/intel/compiler/test_vec4_cmod_propagation.cpp
@@ -31,7 +31,7 @@
using namespace brw;
-class cmod_propagation_test : public ::testing::Test {
+class cmod_propagation_vec4_test : public ::testing::Test {
virtual void SetUp();
virtual void TearDown();
@@ -96,7 +96,7 @@ protected:
};
-void cmod_propagation_test::SetUp()
+void cmod_propagation_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
@@ -113,7 +113,7 @@ void cmod_propagation_test::SetUp()
devinfo->verx10 = devinfo->ver * 10;
}
-void cmod_propagation_test::TearDown()
+void cmod_propagation_vec4_test::TearDown()
{
delete v;
v = NULL;
@@ -152,7 +152,7 @@ cmod_propagation(vec4_visitor *v)
return ret;
}
-TEST_F(cmod_propagation_test, basic)
+TEST_F(cmod_propagation_vec4_test, basic)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::float_type);
@@ -188,7 +188,7 @@ TEST_F(cmod_propagation_test, basic)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
}
-TEST_F(cmod_propagation_test, basic_different_dst_writemask)
+TEST_F(cmod_propagation_vec4_test, basic_different_dst_writemask)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::float_type);
@@ -225,7 +225,7 @@ TEST_F(cmod_propagation_test, basic_different_dst_writemask)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, andz_one)
+TEST_F(cmod_propagation_vec4_test, andz_one)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::int_type);
@@ -261,7 +261,7 @@ TEST_F(cmod_propagation_test, andz_one)
EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, non_cmod_instruction)
+TEST_F(cmod_propagation_vec4_test, non_cmod_instruction)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::uint_type);
@@ -294,7 +294,7 @@ TEST_F(cmod_propagation_test, non_cmod_instruction)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, intervening_flag_write)
+TEST_F(cmod_propagation_vec4_test, intervening_flag_write)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::float_type);
@@ -333,7 +333,7 @@ TEST_F(cmod_propagation_test, intervening_flag_write)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
-TEST_F(cmod_propagation_test, intervening_flag_read)
+TEST_F(cmod_propagation_vec4_test, intervening_flag_read)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest0 = dst_reg(v, glsl_type::float_type);
@@ -373,7 +373,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
-TEST_F(cmod_propagation_test, intervening_dest_write)
+TEST_F(cmod_propagation_vec4_test, intervening_dest_write)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
@@ -414,7 +414,7 @@ TEST_F(cmod_propagation_test, intervening_dest_write)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
-TEST_F(cmod_propagation_test, intervening_flag_read_same_value)
+TEST_F(cmod_propagation_vec4_test, intervening_flag_read_same_value)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest0 = dst_reg(v, glsl_type::float_type);
@@ -456,7 +456,7 @@ TEST_F(cmod_propagation_test, intervening_flag_read_same_value)
EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate);
}
-TEST_F(cmod_propagation_test, negate)
+TEST_F(cmod_propagation_vec4_test, negate)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::float_type);
@@ -492,7 +492,7 @@ TEST_F(cmod_propagation_test, negate)
EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod);
}
-TEST_F(cmod_propagation_test, movnz)
+TEST_F(cmod_propagation_vec4_test, movnz)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::float_type);
@@ -528,7 +528,7 @@ TEST_F(cmod_propagation_test, movnz)
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
}
-TEST_F(cmod_propagation_test, different_types_cmod_with_zero)
+TEST_F(cmod_propagation_vec4_test, different_types_cmod_with_zero)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::int_type);
@@ -563,7 +563,7 @@ TEST_F(cmod_propagation_test, different_types_cmod_with_zero)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, andnz_non_one)
+TEST_F(cmod_propagation_vec4_test, andnz_non_one)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::int_type);
@@ -601,7 +601,7 @@ TEST_F(cmod_propagation_test, andnz_non_one)
/* Note that basic is using glsl_type:float types, while this one is using
* glsl_type::vec4 */
-TEST_F(cmod_propagation_test, basic_vec4)
+TEST_F(cmod_propagation_vec4_test, basic_vec4)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
@@ -634,7 +634,7 @@ TEST_F(cmod_propagation_test, basic_vec4)
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod);
}
-TEST_F(cmod_propagation_test, basic_vec4_different_dst_writemask)
+TEST_F(cmod_propagation_vec4_test, basic_vec4_different_dst_writemask)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
@@ -671,7 +671,7 @@ TEST_F(cmod_propagation_test, basic_vec4_different_dst_writemask)
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, mad_one_component_vec4)
+TEST_F(cmod_propagation_vec4_test, mad_one_component_vec4)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
@@ -713,7 +713,7 @@ TEST_F(cmod_propagation_test, mad_one_component_vec4)
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod);
}
-TEST_F(cmod_propagation_test, mad_more_one_component_vec4)
+TEST_F(cmod_propagation_vec4_test, mad_more_one_component_vec4)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
@@ -756,7 +756,7 @@ TEST_F(cmod_propagation_test, mad_more_one_component_vec4)
EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, cmp_mov_vec4)
+TEST_F(cmod_propagation_vec4_test, cmp_mov_vec4)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::ivec4_type);
@@ -797,7 +797,7 @@ TEST_F(cmod_propagation_test, cmp_mov_vec4)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
}
-TEST_F(cmod_propagation_test, mul_cmp_different_channels_vec4)
+TEST_F(cmod_propagation_vec4_test, mul_cmp_different_channels_vec4)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
@@ -834,7 +834,7 @@ TEST_F(cmod_propagation_test, mul_cmp_different_channels_vec4)
EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, add_cmp_same_dst_writemask)
+TEST_F(cmod_propagation_vec4_test, add_cmp_same_dst_writemask)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::vec4_type);
@@ -869,7 +869,7 @@ TEST_F(cmod_propagation_test, add_cmp_same_dst_writemask)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod);
}
-TEST_F(cmod_propagation_test, add_cmp_different_dst_writemask)
+TEST_F(cmod_propagation_vec4_test, add_cmp_different_dst_writemask)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest = dst_reg(v, glsl_type::float_type);
@@ -906,7 +906,7 @@ TEST_F(cmod_propagation_test, add_cmp_different_dst_writemask)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, prop_across_sel_gfx7)
+TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx7)
{
const vec4_builder bld = vec4_builder(v).at_end();
dst_reg dest1 = dst_reg(v, glsl_type::float_type);
@@ -951,7 +951,7 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx7)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod);
}
-TEST_F(cmod_propagation_test, prop_across_sel_gfx5)
+TEST_F(cmod_propagation_vec4_test, prop_across_sel_gfx5)
{
devinfo->ver = 5;
devinfo->verx10 = devinfo->ver * 10;
@@ -1005,7 +1005,7 @@ TEST_F(cmod_propagation_test, prop_across_sel_gfx5)
EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod);
}
-TEST_F(cmod_propagation_test, prop_into_sel_gfx5)
+TEST_F(cmod_propagation_vec4_test, prop_into_sel_gfx5)
{
devinfo->ver = 5;
devinfo->verx10 = devinfo->ver * 10;
diff --git a/src/intel/compiler/test_vec4_copy_propagation.cpp b/src/intel/compiler/test_vec4_copy_propagation.cpp
index 9be6942eb16..3b3a8051cde 100644
--- a/src/intel/compiler/test_vec4_copy_propagation.cpp
+++ b/src/intel/compiler/test_vec4_copy_propagation.cpp
@@ -27,7 +27,7 @@
using namespace brw;
-class copy_propagation_test : public ::testing::Test {
+class copy_propagation_vec4_test : public ::testing::Test {
virtual void SetUp();
virtual void TearDown();
@@ -86,7 +86,7 @@ protected:
};
-void copy_propagation_test::SetUp()
+void copy_propagation_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
@@ -103,7 +103,7 @@ void copy_propagation_test::SetUp()
devinfo->verx10 = devinfo->ver * 10;
}
-void copy_propagation_test::TearDown()
+void copy_propagation_vec4_test::TearDown()
{
delete v;
v = NULL;
@@ -132,7 +132,7 @@ copy_propagation(vec4_visitor *v)
}
}
-TEST_F(copy_propagation_test, test_swizzle_swizzle)
+TEST_F(copy_propagation_vec4_test, test_swizzle_swizzle)
{
dst_reg a = dst_reg(v, glsl_type::vec4_type);
dst_reg b = dst_reg(v, glsl_type::vec4_type);
@@ -161,7 +161,7 @@ TEST_F(copy_propagation_test, test_swizzle_swizzle)
SWIZZLE_Y));
}
-TEST_F(copy_propagation_test, test_swizzle_writemask)
+TEST_F(copy_propagation_vec4_test, test_swizzle_writemask)
{
dst_reg a = dst_reg(v, glsl_type::vec4_type);
dst_reg b = dst_reg(v, glsl_type::vec4_type);
diff --git a/src/intel/compiler/test_vec4_dead_code_eliminate.cpp b/src/intel/compiler/test_vec4_dead_code_eliminate.cpp
index 4daf7f7fac0..3e22afd9219 100644
--- a/src/intel/compiler/test_vec4_dead_code_eliminate.cpp
+++ b/src/intel/compiler/test_vec4_dead_code_eliminate.cpp
@@ -27,7 +27,7 @@
using namespace brw;
-class dead_code_eliminate_test : public ::testing::Test {
+class dead_code_eliminate_vec4_test : public ::testing::Test {
virtual void SetUp();
virtual void TearDown();
@@ -86,7 +86,7 @@ protected:
};
-void dead_code_eliminate_test::SetUp()
+void dead_code_eliminate_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
@@ -103,7 +103,7 @@ void dead_code_eliminate_test::SetUp()
devinfo->verx10 = devinfo->ver * 10;
}
-void dead_code_eliminate_test::TearDown()
+void dead_code_eliminate_vec4_test::TearDown()
{
delete v;
v = NULL;
@@ -131,7 +131,7 @@ dead_code_eliminate(vec4_visitor *v)
}
}
-TEST_F(dead_code_eliminate_test, some_dead_channels_all_flags_used)
+TEST_F(dead_code_eliminate_vec4_test, some_dead_channels_all_flags_used)
{
const vec4_builder bld = vec4_builder(v).at_end();
src_reg r1 = src_reg(v, glsl_type::vec4_type);
diff --git a/src/intel/compiler/test_vec4_register_coalesce.cpp b/src/intel/compiler/test_vec4_register_coalesce.cpp
index b4c1e07dbf7..323aad8029c 100644
--- a/src/intel/compiler/test_vec4_register_coalesce.cpp
+++ b/src/intel/compiler/test_vec4_register_coalesce.cpp
@@ -29,7 +29,7 @@ using namespace brw;
#define register_coalesce(v) _register_coalesce(v, __func__)
-class register_coalesce_test : public ::testing::Test {
+class register_coalesce_vec4_test : public ::testing::Test {
virtual void SetUp();
virtual void TearDown();
@@ -89,7 +89,7 @@ protected:
};
-void register_coalesce_test::SetUp()
+void register_coalesce_vec4_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
@@ -107,7 +107,7 @@ void register_coalesce_test::SetUp()
devinfo->verx10 = devinfo->ver * 10;
}
-void register_coalesce_test::TearDown()
+void register_coalesce_vec4_test::TearDown()
{
delete v;
v = NULL;
@@ -135,7 +135,7 @@ _register_coalesce(vec4_visitor *v, const char *func)
}
}
-TEST_F(register_coalesce_test, test_compute_to_mrf)
+TEST_F(register_coalesce_vec4_test, test_compute_to_mrf)
{
src_reg something = src_reg(v, glsl_type::float_type);
dst_reg temp = dst_reg(v, glsl_type::float_type);
@@ -154,7 +154,7 @@ TEST_F(register_coalesce_test, test_compute_to_mrf)
}
-TEST_F(register_coalesce_test, test_multiple_use)
+TEST_F(register_coalesce_vec4_test, test_multiple_use)
{
src_reg something = src_reg(v, glsl_type::float_type);
dst_reg temp = dst_reg(v, glsl_type::vec4_type);
@@ -180,7 +180,7 @@ TEST_F(register_coalesce_test, test_multiple_use)
EXPECT_NE(mul->dst.file, MRF);
}
-TEST_F(register_coalesce_test, test_dp4_mrf)
+TEST_F(register_coalesce_vec4_test, test_dp4_mrf)
{
src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
@@ -201,7 +201,7 @@ TEST_F(register_coalesce_test, test_dp4_mrf)
EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
}
-TEST_F(register_coalesce_test, test_dp4_grf)
+TEST_F(register_coalesce_vec4_test, test_dp4_grf)
{
src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
@@ -227,7 +227,7 @@ TEST_F(register_coalesce_test, test_dp4_grf)
EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
}
-TEST_F(register_coalesce_test, test_channel_mul_grf)
+TEST_F(register_coalesce_vec4_test, test_channel_mul_grf)
{
src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
More information about the mesa-commit
mailing list