Mesa (main): aco: fix invalid IR generated for b2f64 when the dest is a VGPR

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Module: Mesa
Branch: main
Commit: e3cbb0eb6a7b998f33d5175274fd3a4bf4fd5973
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3cbb0eb6a7b998f33d5175274fd3a4bf4fd5973

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Tue Oct 19 14:01:45 2021 +0200

aco: fix invalid IR generated for b2f64 when the dest is a VGPR

Fixes few 64-bit piglit tests with Zink.

Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13435>

---

 src/amd/compiler/aco_instruction_selection.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 1ace1605172..743fed4a7d8 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -3038,7 +3038,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand::c32(0x3f800000u),
                   Operand::zero(), bld.scc(src));
       } else if (dst.regClass() == v2) {
-         Temp one = bld.copy(bld.def(v2), Operand::c32(0x3FF00000u));
+         Temp one = bld.copy(bld.def(v1), Operand::c32(0x3FF00000u));
          Temp upper =
             bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand::zero(), one, src);
          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand::zero(), upper);