Mesa (main): iris: Add missed tile flush flag

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Module: Mesa
Branch: main
Commit: 0523607ebb108d8c90bbda9c6564b66a0a6250e6
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0523607ebb108d8c90bbda9c6564b66a0a6250e6

Author: Mykhailo Skorokhodov <mykhailo.skorokhodov at globallogic.com>
Date:   Wed Sep 22 16:03:23 2021 +0300

iris: Add missed tile flush flag

Without adding `PIPE_CONTROL_TILE_CACHE_FLUSH` into `iris_emit_pipe_control`
gen12+ (UHD 750 in my case) has issues with textures.

Related-to: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5029
Fixes: c85ea824('iris: reduce redundant tile cache flushes')

Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov at globallogic.com>
Reviewed-by: Felix DeGrood <felix.j.degrood at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12979>

---

 src/gallium/drivers/iris/iris_pipe_control.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c
index 33c904740da..df6814fd32c 100644
--- a/src/gallium/drivers/iris/iris_pipe_control.c
+++ b/src/gallium/drivers/iris/iris_pipe_control.c
@@ -353,7 +353,8 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags)
 
    if (flags & (PIPE_BARRIER_TEXTURE | PIPE_BARRIER_FRAMEBUFFER)) {
       bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
-              PIPE_CONTROL_RENDER_TARGET_FLUSH;
+              PIPE_CONTROL_RENDER_TARGET_FLUSH |
+              PIPE_CONTROL_TILE_CACHE_FLUSH;
    }
 
    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {