Mesa (staging/21.2): anv: fix push constant lowering with bindless shaders
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Wed Oct 27 21:53:15 UTC 2021
Module: Mesa
Branch: staging/21.2
Commit: a29d40b5639ce8ee157ee4dc5ac0d2f8ab4f38f7
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a29d40b5639ce8ee157ee4dc5ac0d2f8ab4f38f7
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Tue Oct 26 14:27:18 2021 +0300
anv: fix push constant lowering with bindless shaders
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 9fa1cdfe7ffd ("intel/rt: Implement push constants as global memory reads")
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13529>
(cherry picked from commit a6031cd9bd409c793c3a2928eaf9f04f09d2f55a)
---
.pick_status.json | 2 +-
src/intel/vulkan/anv_nir_compute_push_layout.c | 13 +++++++++++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index 5e5ae3fbf57..253825d125d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -346,7 +346,7 @@
"description": "anv: fix push constant lowering with bindless shaders",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": "9fa1cdfe7ffd9e7ebd83055e2008f3e4b8ada549"
},
diff --git a/src/intel/vulkan/anv_nir_compute_push_layout.c b/src/intel/vulkan/anv_nir_compute_push_layout.c
index 526e1a48f0b..66b8cd029c1 100644
--- a/src/intel/vulkan/anv_nir_compute_push_layout.c
+++ b/src/intel/vulkan/anv_nir_compute_push_layout.c
@@ -149,12 +149,21 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
switch (intrin->intrinsic) {
- case nir_intrinsic_load_push_constant:
+ case nir_intrinsic_load_push_constant: {
+ /* With bindless shaders we load uniforms with SEND
+ * messages. All the push constants are located after the
+ * RT_DISPATCH_GLOBALS. We just need to add the offset to
+ * the address right after RT_DISPATCH_GLOBALS (see
+ * brw_nir_lower_rt_intrinsics.c).
+ */
+ unsigned base_offset =
+ brw_shader_stage_is_bindless(nir->info.stage) ? 0 : push_start;
intrin->intrinsic = nir_intrinsic_load_uniform;
nir_intrinsic_set_base(intrin,
nir_intrinsic_base(intrin) -
- push_start);
+ base_offset);
break;
+ }
case nir_intrinsic_load_desc_set_address_intel: {
b->cursor = nir_before_instr(&intrin->instr);
More information about the mesa-commit
mailing list