Mesa (main): radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers

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Module: Mesa
Branch: main
Commit: b92e109ac6da0a4310774fb120db3bf29d14bda7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b92e109ac6da0a4310774fb120db3bf29d14bda7

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed Aug 11 02:49:33 2021 -0400

radeonsi: correctly use cs instead of gfx_cs in build pm4 helpers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>

---

 src/gallium/drivers/radeonsi/si_build_pm4.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h
index 1dd562971c5..b96c9201fb7 100644
--- a/src/gallium/drivers/radeonsi/si_build_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
@@ -168,7 +168,7 @@
    __value &= mask; \
    if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
        sctx->tracked_regs.reg_value[reg] != __value) { \
-      radeon_set_context_reg_rmw(&sctx->gfx_cs, offset, __value, mask); \
+      radeon_set_context_reg_rmw(cs, offset, __value, mask); \
       sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
       sctx->tracked_regs.reg_value[reg] = __value; \
    } \
@@ -179,7 +179,7 @@
    unsigned __value = val; \
    if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
        sctx->tracked_regs.reg_value[reg] != __value) { \
-      radeon_set_context_reg(&sctx->gfx_cs, offset, __value); \
+      radeon_set_context_reg(cs, offset, __value); \
       sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
       sctx->tracked_regs.reg_value[reg] = __value; \
    } \
@@ -196,7 +196,7 @@
    if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x3) != 0x3 || \
        sctx->tracked_regs.reg_value[reg] != __value1 || \
        sctx->tracked_regs.reg_value[(reg) + 1] != __value2) { \
-      radeon_set_context_reg_seq(&sctx->gfx_cs, offset, 2); \
+      radeon_set_context_reg_seq(cs, offset, 2); \
       radeon_emit(cs, __value1); \
       radeon_emit(cs, __value2); \
       sctx->tracked_regs.reg_value[reg] = __value1; \
@@ -214,7 +214,7 @@
        sctx->tracked_regs.reg_value[reg] != __value1 || \
        sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
        sctx->tracked_regs.reg_value[(reg) + 2] != __value3) { \
-      radeon_set_context_reg_seq(&sctx->gfx_cs, offset, 3); \
+      radeon_set_context_reg_seq(cs, offset, 3); \
       radeon_emit(cs, __value1); \
       radeon_emit(cs, __value2); \
       radeon_emit(cs, __value3); \
@@ -235,7 +235,7 @@
        sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
        sctx->tracked_regs.reg_value[(reg) + 2] != __value3 || \
        sctx->tracked_regs.reg_value[(reg) + 3] != __value4) { \
-      radeon_set_context_reg_seq(&sctx->gfx_cs, offset, 4); \
+      radeon_set_context_reg_seq(cs, offset, 4); \
       radeon_emit(cs, __value1); \
       radeon_emit(cs, __value2); \
       radeon_emit(cs, __value3); \
@@ -277,7 +277,7 @@
 
 #define radeon_emit_one_32bit_pointer(sctx, desc, sh_base) do { \
    unsigned sh_offset = (sh_base) + (desc)->shader_userdata_offset; \
-   radeon_set_sh_reg_seq(&sctx->gfx_cs, sh_offset, 1); \
+   radeon_set_sh_reg_seq(cs, sh_offset, 1); \
    radeon_emit_32bit_pointer(sctx->screen, cs, (desc)->gpu_address); \
 } while (0)