Mesa (main): intel/fs: Add the URB fence message
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Wed Sep 29 21:12:21 UTC 2021
Module: Mesa
Branch: main
Commit: e6a9501aa2732b356924be96c13b27bc95c4fd37
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6a9501aa2732b356924be96c13b27bc95c4fd37
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Sep 15 16:21:14 2021 -0500
intel/fs: Add the URB fence message
When they re-arranged all the dataport stuff and added the LSC, doing
URB fencing through the dataport no longer makes sense. Instead, there
is now a fence message on the URB shared function.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Tested-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13092>
---
src/intel/compiler/brw_disasm.c | 5 +++--
src/intel/compiler/brw_eu.h | 7 +++++++
src/intel/compiler/brw_eu_defines.h | 1 +
src/intel/compiler/brw_eu_emit.c | 23 ++++++++++++++---------
src/intel/compiler/brw_ir_performance.cpp | 1 +
5 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 1ce0ea27154..acbe9d6f94d 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -562,7 +562,8 @@ static const char *const gfx7_urb_opcode[] = {
[GFX8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gfx8+ */
[GFX8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gfx8+ */
[GFX8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gfx8+ */
- /* [9-15] - reserved */
+ [GFX125_URB_OPCODE_FENCE] = "fence", /* Gfx12.5+ */
+ /* [10-15] - reserved */
};
static const char *const urb_swizzle[4] = {
@@ -2189,7 +2190,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
opcode == GFX8_URB_OPCODE_SIMD8_READ) {
if (brw_inst_urb_channel_mask_present(devinfo, inst))
string(file, " masked");
- } else {
+ } else if (opcode != GFX125_URB_OPCODE_FENCE) {
err |= control(file, "urb swizzle", urb_swizzle,
brw_inst_urb_swizzle_control(devinfo, inst),
&space);
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 995e6d841ba..04256257533 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -375,6 +375,13 @@ brw_urb_desc_msg_type(ASSERTED const struct intel_device_info *devinfo,
return GET_BITS(desc, 3, 0);
}
+static inline uint32_t
+brw_urb_fence_desc(const struct intel_device_info *devinfo)
+{
+ assert(devinfo->has_lsc);
+ return brw_urb_desc(devinfo, GFX125_URB_OPCODE_FENCE, false, false, 0);
+}
+
/**
* Construct a message descriptor immediate with the specified sampler
* function controls.
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 03263e94174..1732abbe7df 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -1608,6 +1608,7 @@ enum brw_message_target {
#define GFX8_URB_OPCODE_ATOMIC_ADD 6
#define GFX8_URB_OPCODE_SIMD8_WRITE 7
#define GFX8_URB_OPCODE_SIMD8_READ 8
+#define GFX125_URB_OPCODE_FENCE 9
#define BRW_URB_SWIZZLE_NONE 0
#define BRW_URB_SWIZZLE_INTERLEAVE 1
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ad276e60e60..a8e19cbf0c9 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3255,17 +3255,22 @@ gfx12_set_memory_fence_message(struct brw_codegen *p,
brw_inst_set_sfid(p->devinfo, insn, sfid);
- enum lsc_fence_scope scope = LSC_FENCE_THREADGROUP;
- enum lsc_flush_type flush_type = LSC_FLUSH_TYPE_NONE;
+ if (sfid == BRW_SFID_URB) {
+ brw_set_desc(p, insn, brw_urb_fence_desc(p->devinfo) |
+ brw_message_desc(p->devinfo, mlen, rlen, false));
+ } else {
+ enum lsc_fence_scope scope = LSC_FENCE_THREADGROUP;
+ enum lsc_flush_type flush_type = LSC_FLUSH_TYPE_NONE;
- if (sfid == GFX12_SFID_TGM) {
- scope = LSC_FENCE_TILE;
- flush_type = LSC_FLUSH_TYPE_EVICT;
- }
+ if (sfid == GFX12_SFID_TGM) {
+ scope = LSC_FENCE_TILE;
+ flush_type = LSC_FLUSH_TYPE_EVICT;
+ }
- brw_set_desc(p, insn, lsc_fence_msg_desc(p->devinfo, scope,
- flush_type, false) |
- brw_message_desc(p->devinfo, mlen, rlen, false));
+ brw_set_desc(p, insn, lsc_fence_msg_desc(p->devinfo, scope,
+ flush_type, false) |
+ brw_message_desc(p->devinfo, mlen, rlen, false));
+ }
}
void
diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp
index f04694f8971..2a7dc787afe 100644
--- a/src/intel/compiler/brw_ir_performance.cpp
+++ b/src/intel/compiler/brw_ir_performance.cpp
@@ -946,6 +946,7 @@ namespace {
else
abort();
+ case BRW_SFID_URB:
case GFX7_SFID_DATAPORT_DATA_CACHE:
case GFX12_SFID_SLM:
case GFX12_SFID_TGM:
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