Mesa (main): radv: rework the workaround that disables DCC for incompatible copies
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gitlab-mirror at kemper.freedesktop.org
Fri Apr 1 07:01:28 UTC 2022
Module: Mesa
Branch: main
Commit: 9309c3d8872ce71e0a3522d2132488d3c0551ab2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9309c3d8872ce71e0a3522d2132488d3c0551ab2
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Mar 28 14:00:43 2022 +0200
radv: rework the workaround that disables DCC for incompatible copies
Rely on the image view to avoid using an extra structure for the
render pass. This will allow to convert the meta operations to
dynamic rendering.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15612>
---
src/amd/vulkan/radv_cmd_buffer.c | 20 ++++++++------------
src/amd/vulkan/radv_device.c | 2 +-
src/amd/vulkan/radv_image.c | 1 +
src/amd/vulkan/radv_meta_blit.c | 9 +++------
src/amd/vulkan/radv_meta_blit2d.c | 14 ++++++--------
src/amd/vulkan/radv_meta_clear.c | 3 +--
src/amd/vulkan/radv_meta_decompress.c | 3 +--
src/amd/vulkan/radv_meta_fast_clear.c | 3 +--
src/amd/vulkan/radv_meta_resolve.c | 3 +--
src/amd/vulkan/radv_meta_resolve_fs.c | 3 +--
src/amd/vulkan/radv_private.h | 11 ++++-------
11 files changed, 28 insertions(+), 44 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 9d71c441424..64ad93eb350 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1755,7 +1755,7 @@ radv_emit_color_write_enable(struct radv_cmd_buffer *cmd_buffer)
static void
radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
struct radv_color_buffer_info *cb, struct radv_image_view *iview,
- VkImageLayout layout, bool in_render_loop, bool disable_dcc)
+ VkImageLayout layout, bool in_render_loop)
{
bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;
uint32_t cb_color_info = cb->cb_color_info;
@@ -1764,8 +1764,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
if (!radv_layout_dcc_compressed(
cmd_buffer->device, image, iview->base_mip, layout, in_render_loop,
radv_image_queue_family_mask(image, cmd_buffer->qf,
- cmd_buffer->qf)) ||
- disable_dcc) {
+ cmd_buffer->qf))) {
cb_color_info &= C_028C70_DCC_ENABLE;
}
@@ -2524,7 +2523,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout,
- in_render_loop, cmd_buffer->state.attachments[idx].disable_dcc);
+ in_render_loop);
radv_load_color_clear_metadata(cmd_buffer, iview, i);
@@ -4315,8 +4314,7 @@ radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,
static VkResult
radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer, struct radv_render_pass *pass,
- const VkRenderPassBeginInfo *info,
- const struct radv_extra_render_pass_begin_info *extra)
+ const VkRenderPassBeginInfo *info)
{
struct radv_cmd_state *state = &cmd_buffer->state;
const struct VkRenderPassAttachmentBeginInfo *attachment_info = NULL;
@@ -4373,7 +4371,6 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer, struct radv
state->attachments[i].current_layout = att->initial_layout;
state->attachments[i].current_in_render_loop = false;
state->attachments[i].current_stencil_layout = att->stencil_initial_layout;
- state->attachments[i].disable_dcc = extra && extra->disable_dcc;
state->attachments[i].sample_location.count = 0;
struct radv_image_view *iview;
@@ -4625,7 +4622,7 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi
}
if (cmd_buffer->state.framebuffer) {
- result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL, NULL);
+ result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
if (result != VK_SUCCESS)
return result;
}
@@ -5976,8 +5973,7 @@ radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
void
radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
- const VkRenderPassBeginInfo *pRenderPassBegin,
- const struct radv_extra_render_pass_begin_info *extra_info)
+ const VkRenderPassBeginInfo *pRenderPassBegin)
{
RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
@@ -5987,7 +5983,7 @@ radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->state.pass = pass;
cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
- result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin, extra_info);
+ result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
if (result != VK_SUCCESS)
return;
@@ -6003,7 +5999,7 @@ radv_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
- radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBeginInfo, NULL);
+ radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBeginInfo);
radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
}
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 12c15d41d81..3480ee843ac 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -5716,7 +5716,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
!(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
- if (radv_dcc_enabled(iview->image, iview->base_mip))
+ if (radv_dcc_enabled(iview->image, iview->base_mip) && !iview->disable_dcc_mrt)
cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 10890413a3f..a8cac871be2 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -2168,6 +2168,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
}
iview->support_fast_clear = radv_image_view_can_fast_clear(device, iview);
+ iview->disable_dcc_mrt = extra_create_info ? extra_create_info->disable_dcc_mrt : false;
bool disable_compression = extra_create_info ? extra_create_info->disable_compression : false;
bool enable_compression = extra_create_info ? extra_create_info->enable_compression : false;
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index bb00b1652a5..ca5e5bd7cf7 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -295,8 +295,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
switch (src_image->type) {
case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.pipeline_1d_src[fs_key];
@@ -327,8 +326,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
switch (src_image->type) {
case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.depth_only_1d_pipeline;
@@ -359,8 +357,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
switch (src_image->type) {
case VK_IMAGE_TYPE_1D:
pipeline = &device->meta_state.blit.stencil_only_1d_pipeline;
diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c
index ccdc2ea2ea4..0e081b57ffd 100644
--- a/src/amd/vulkan/radv_meta_blit2d.c
+++ b/src/amd/vulkan/radv_meta_blit2d.c
@@ -73,7 +73,9 @@ create_iview(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *s
.baseArrayLayer = surf->layer,
.layerCount = 1},
},
- NULL);
+ &(struct radv_image_view_extra_create_info){
+ .disable_dcc_mrt = surf->disable_compression
+ });
}
static void
@@ -291,9 +293,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- &(struct radv_extra_render_pass_begin_info){.disable_dcc =
- dst->disable_compression});
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
@@ -327,8 +327,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
@@ -363,8 +362,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 06e55b5c956..525890ef84f 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -2240,8 +2240,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im
.framebuffer = fb,
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
diff --git a/src/amd/vulkan/radv_meta_decompress.c b/src/amd/vulkan/radv_meta_decompress.c
index 288e355fcf2..cb70e569e92 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -532,8 +532,7 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i
}},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c
index ef3747e8242..3e5a496fe7a 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -601,8 +601,7 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i
}},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
diff --git a/src/amd/vulkan/radv_meta_resolve.c b/src/amd/vulkan/radv_meta_resolve.c
index fe3185ccd8a..7eceecd0b91 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -583,8 +583,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
}},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index f976df2339d..c531ded2e4d 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -1042,8 +1042,7 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
},
.clearValueCount = 0,
.pClearValues = NULL,
- },
- NULL);
+ });
radv_cmd_buffer_set_subpass(cmd_buffer, &cmd_buffer->state.pass->subpasses[0]);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e0473e85412..b30c65aff71 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1360,7 +1360,6 @@ struct radv_attachment_state {
VkImageLayout current_layout;
VkImageLayout current_stencil_layout;
bool current_in_render_loop;
- bool disable_dcc;
struct radv_sample_locations_state sample_location;
union {
@@ -2379,6 +2378,8 @@ struct radv_image_view {
/* Whether the image iview supports fast clear. */
bool support_fast_clear;
+ bool disable_dcc_mrt;
+
union radv_descriptor descriptor;
/* Descriptor for use as a storage image as opposed to a sampled image.
@@ -2427,6 +2428,7 @@ bool radv_android_gralloc_supports_format(VkFormat format, VkImageUsageFlagBits
struct radv_image_view_extra_create_info {
bool disable_compression;
bool enable_compression;
+ bool disable_dcc_mrt;
};
void radv_image_view_init(struct radv_image_view *view, struct radv_device *device,
@@ -2779,13 +2781,8 @@ si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
}
}
-struct radv_extra_render_pass_begin_info {
- bool disable_dcc;
-};
-
void radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,
- const VkRenderPassBeginInfo *pRenderPassBegin,
- const struct radv_extra_render_pass_begin_info *extra_info);
+ const VkRenderPassBeginInfo *pRenderPassBegin);
void radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer);
static inline uint32_t
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