Mesa (main): pan/va: Add indirect LEA_{ATTR, TEX}

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Module: Mesa
Branch: main
Commit: 1f4cb6d99fd6b04d192369d4bb715e7c0548dec4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f4cb6d99fd6b04d192369d4bb715e7c0548dec4

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Wed Mar 30 12:45:07 2022 -0400

pan/va: Add indirect LEA_{ATTR, TEX}

For parity with Bifrost. We might need these for images.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15756>

---

 src/panfrost/bifrost/valhall/ISA.xml | 37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index e276d6311f5..b439c22a6ce 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -970,6 +970,22 @@
     <imm name="index" start="20" size="4"/>
   </ins>
 
+  <ins name="LEA_ATTR" title="Load effective address of image texel" opcode="0x77" opcode2="0" unit="LS">
+    <desc>
+      Load the effective address of an attribute specified with the
+      given index. Returns three staging register: the low/high
+      32-bits of the address and the internal conversion descriptor.
+    </desc>
+    <vecsize/>
+    <slot/>
+    <sr_count/>
+    <mod name="descriptor_type" start="128" size="1" implied="true"/>
+    <sr write="true"/>
+    <src>Vertex index</src>
+    <src>Instance index</src>
+    <src>Attribute index and table</src>
+  </ins>
+
   <ins name="LEA_TEX_IMM" title="Load effective address of image texel" opcode="0x67" opcode2="1" unit="LS">
     <desc>
       Load the effective address of a texel from the image specified with the
@@ -992,6 +1008,27 @@
     <imm name="index" start="20" size="4"/>
   </ins>
 
+  <ins name="LEA_TEX" title="Load effective address of image texel" opcode="0x77" opcode2="1" unit="LS">
+    <desc>
+      Load the effective address of a texel from the image specified with the
+      given index. Returns three staging register: the low/high
+      32-bits of the address and the internal conversion descriptor. The format
+      of the internal conversion descriptor is compatible with Bifrost but
+      omits the register format, as this is specified with the ST_CVT
+      instruction on Valhall.
+
+      Coordinates are specified as 16-bit integers, packed into 32-bit sources.
+    </desc>
+    <vecsize/>
+    <slot/>
+    <sr_count/>
+    <mod name="descriptor_type" start="128" size="1" implied="true"/>
+    <sr write="true"/>
+    <src>X/Y coordinates (16:16)</src>
+    <src>Z/W coordinates (16:16)</src>
+    <src>Index and table</src>
+  </ins>
+
   <ins name="LD_BUFFER.i8" title="Global memory load" opcode="0x6a" opcode2="0" unit="LS">
     <desc>
       Loads a buffer descriptor. If bits 25...31 of the mode descriptor are