Mesa (main): pan/bi: Lower gl_PointSize to FP16 on Valhall

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Module: Mesa
Branch: main
Commit: 9497a6a3c9bcf6fac5dc29eb2d662bc12a3db4af
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9497a6a3c9bcf6fac5dc29eb2d662bc12a3db4af

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Fri Jan 28 12:07:41 2022 -0500

pan/bi: Lower gl_PointSize to FP16 on Valhall

It is unclear if FP32 point sizes are supported on Valhall -- I can't get the
DDK to use them at any rate. Always lower them to FP16 and store them as FP16
for hardware use.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15793>

---

 src/panfrost/bifrost/bifrost_compile.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c
index 65dec9f52f7..32a3691882e 100644
--- a/src/panfrost/bifrost/bifrost_compile.c
+++ b/src/panfrost/bifrost/bifrost_compile.c
@@ -4380,6 +4380,11 @@ bi_finalize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
                 NIR_PASS_V(nir, nir_lower_mediump_io, nir_var_shader_out,
                                 ~0, false);
         } else {
+                if (gpu_id >= 0x9000) {
+                        NIR_PASS_V(nir, nir_lower_mediump_io, nir_var_shader_out,
+                                        BITFIELD64_BIT(VARYING_SLOT_PSIZ), false);
+                }
+
                 struct hash_table_u64 *stores = _mesa_hash_table_u64_create(NULL);
                 NIR_PASS_V(nir, nir_shader_instructions_pass,
                                 bifrost_nir_lower_store_component,