Mesa (main): iris: Add a separate PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE bit

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Module: Mesa
Branch: main
Commit: 8cd7e94ecaefbb4dfa7a55dbb404a9dbb36deee0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cd7e94ecaefbb4dfa7a55dbb404a9dbb36deee0

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Sat Apr  9 02:19:15 2022 -0700

iris: Add a separate PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE bit

This will let us use it without performing a VF cache invalidation,
should we want to do that.

Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

---

 src/gallium/drivers/iris/iris_context.h |  1 +
 src/gallium/drivers/iris/iris_state.c   | 17 +++++++++++++----
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index f9924f70d66..91f128d121b 100644
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -342,6 +342,7 @@ enum pipe_control_flags
    PIPE_CONTROL_TILE_CACHE_FLUSH                = (1 << 25),
    PIPE_CONTROL_FLUSH_HDC                       = (1 << 26),
    PIPE_CONTROL_PSS_STALL_SYNC                  = (1 << 27),
+   PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE   = (1 << 28),
 };
 
 #define PIPE_CONTROL_CACHE_FLUSH_BITS \
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 4f04e3928d9..45c60aa8166 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -7741,6 +7741,18 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
    }
 #endif
 
+   /* The "L3 Read Only Cache Invalidation Bit" docs say it "controls the
+    * invalidation of the Geometry streams cached in L3 cache at the top
+    * of the pipe".  In other words, index & vertex data that gets cached
+    * in L3 when VERTEX_BUFFER_STATE::L3BypassDisable is set.
+    *
+    * Normally, invalidating L1/L2 read-only caches also invalidate their
+    * related L3 cachelines, but this isn't the case for the VF cache.
+    * Emulate it by setting the L3 Read Only bit when doing a VF invalidate.
+    */
+   if (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)
+      flags |= PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE;
+
    /* Recursive PIPE_CONTROL workarounds --------------------------------
     * (http://knowyourmeme.com/memes/xzibit-yo-dawg)
     *
@@ -8125,11 +8137,8 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
       pc.StateCacheInvalidationEnable =
          flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 #if GFX_VER >= 12
-      /* Invalidates the L3 cache part in which index & vertex data is loaded
-       * when VERTEX_BUFFER_STATE::L3BypassDisable is set.
-       */
       pc.L3ReadOnlyCacheInvalidationEnable =
-         flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
+         flags & PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE;
 #endif
       pc.VFCacheInvalidationEnable = flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
       pc.ConstantCacheInvalidationEnable =