Mesa (main): iris: Use cache-tracker for draw count flushing

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: bbd5714a7e18225a65de866ed8083c8d9c77e710
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbd5714a7e18225a65de866ed8083c8d9c77e710

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Mar  8 00:07:16 2022 -0800

iris: Use cache-tracker for draw count flushing

We should be using the cache tracker for this.  We can consider
this access IRIS_DOMAIN_OTHER_READ now that it's the catch-all
non-L3-coherent read-only access domain.

Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Rohan Garg <rohan.garg at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15275>

---

 src/gallium/drivers/iris/iris_state.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 58cf5badb72..86266add319 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -7027,14 +7027,11 @@ iris_upload_render_state(struct iris_context *ice,
    } else if (indirect && indirect->count_from_stream_output) {
       struct iris_stream_output_target *so =
          (void *) indirect->count_from_stream_output;
+      struct iris_bo *so_bo = iris_resource_bo(so->offset.res);
 
-      /* XXX: Replace with actual cache tracking */
-      iris_emit_pipe_control_flush(batch,
-                                   "draw count from stream output stall",
-                                   PIPE_CONTROL_CS_STALL);
+      iris_emit_buffer_barrier_for(batch, so_bo, IRIS_DOMAIN_OTHER_READ);
 
-      struct iris_address addr =
-         ro_bo(iris_resource_bo(so->offset.res), so->offset.offset);
+      struct iris_address addr = ro_bo(so_bo, so->offset.offset);
       struct mi_value offset =
          mi_iadd_imm(&b, mi_mem32(addr), -so->base.buffer_offset);
       mi_store(&b, mi_reg32(_3DPRIM_VERTEX_COUNT),