Mesa (staging/22.0): intel/fs: Force destination types on DP4A instructions

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: 7469f9452448bc22cd424b594d0c9b4481173524
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7469f9452448bc22cd424b594d0c9b4481173524

Author: Ian Romanick <ian.d.romanick at intel.com>
Date:   Wed Mar 16 12:56:54 2022 -0700

intel/fs: Force destination types on DP4A instructions

Most of the time, this doesn't matter.  On the versions with _sat, if
the destination type is incorrect, the clamping will not happen
correctly.

Fixes the following CTS tests:

dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_packed_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.all_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_packed_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.limits_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_packed_uu_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_ss_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_su_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_us_v4i8_out32
dEQP-VK.spirv_assembly.instruction.compute.opudotaccsatkhr.small_uu_v4i8_out32

v2: Update anv-tgl-fails.txt.

Reviewed-by: Ivan Briano <ivan.briano at intel.com>
Fixes: 0f809dbf404 ("intel/compiler: Basic support for DP4A instruction")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15417>
(cherry picked from commit 19330eeb1d65c631ce11a0be1cb13437c6c28491)

Conflicts:
	src/intel/ci/anv-tgl-fails.txt

---

 .pick_status.json                 | 2 +-
 src/intel/compiler/brw_fs_nir.cpp | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index a97a5e22658..4c469805eec 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -9228,7 +9228,7 @@
         "description": "intel/fs: Force destination types on DP4A instructions",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 5,
+        "resolution": 1,
         "because_sha": "0f809dbf4048cbd89c5cf28dbb9ab38cc726fe2a"
     },
     {
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 6a3bb21f3c5..16203a047e7 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1889,7 +1889,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
 
    case nir_op_sdot_4x8_iadd:
    case nir_op_sdot_4x8_iadd_sat:
-      inst = bld.DP4A(result,
+      inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_D),
                       retype(op[2], BRW_REGISTER_TYPE_D),
                       retype(op[0], BRW_REGISTER_TYPE_D),
                       retype(op[1], BRW_REGISTER_TYPE_D));
@@ -1900,7 +1900,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
 
    case nir_op_udot_4x8_uadd:
    case nir_op_udot_4x8_uadd_sat:
-      inst = bld.DP4A(result,
+      inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_UD),
                       retype(op[2], BRW_REGISTER_TYPE_UD),
                       retype(op[0], BRW_REGISTER_TYPE_UD),
                       retype(op[1], BRW_REGISTER_TYPE_UD));
@@ -1911,7 +1911,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr,
 
    case nir_op_sudot_4x8_iadd:
    case nir_op_sudot_4x8_iadd_sat:
-      inst = bld.DP4A(result,
+      inst = bld.DP4A(retype(result, BRW_REGISTER_TYPE_D),
                       retype(op[2], BRW_REGISTER_TYPE_D),
                       retype(op[0], BRW_REGISTER_TYPE_D),
                       retype(op[1], BRW_REGISTER_TYPE_UD));