Mesa (main): nouveau: Skip cctl for atomic counters in tgsi

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Module: Mesa
Branch: main
Commit: 8313a9231c9a7e6f649cbd663d1cf2a7b0fbb91d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8313a9231c9a7e6f649cbd663d1cf2a7b0fbb91d

Author: M Henning <drawoc at darkrefraction.com>
Date:   Sat Jan 29 22:20:58 2022 -0500

nouveau: Skip cctl for atomic counters in tgsi

The tgsi path already marked all aliasing loads of atomic counters with
CACHE_CG, so we don't need to emit a cctl. This patch uses the cache
flag on the atomic to model whether the L1 cache needs the stale
values to be flushed or not.

Reviewed-by: Karol Herbst <kherbst at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14386>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp     | 4 ++++
 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 20b9ca8119a..d843d676da0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2962,6 +2962,10 @@ Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp)
          if (ind)
             insn->setIndirect(0, 1, ind);
          insn->subOp = subOp;
+
+         if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER &&
+             code->bufferAtomics[tgsi.getSrc(0).getIndex(0)])
+            insn->cache = nv50_ir::CACHE_CG;
       }
       for (int c = 0; c < 4; ++c)
          if (dst0[c])
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index fbdc1b8f1d0..18e21920a6a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1708,6 +1708,10 @@ bool
 NVC0LoweringPass::handleATOMCctl(Instruction *atom) {
    // Flush L1 cache manually since atomics go directly to L2. This ensures
    // that any later CA reads retrieve the updated data.
+
+   if (atom->cache != nv50_ir::CACHE_CA)
+      return false;
+
    bld.setPosition(atom, true);
 
    Instruction *cctl = bld.mkOp1(OP_CCTL, TYPE_NONE, NULL, atom->getSrc(0));