Mesa (main): nouveau/nir: Disable bitfield ops pre-nvc0.

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Module: Mesa
Branch: main
Commit: 6040107dc1e8374b7be60c0f9704fe593f00cd9b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6040107dc1e8374b7be60c0f9704fe593f00cd9b

Author: Emma Anholt <emma at anholt.net>
Date:   Mon Mar 28 11:21:26 2022 -0700

nouveau/nir: Disable bitfield ops pre-nvc0.

There's no hardware instructions for them until then.  These chips don't
expose the extension provinding the GLSL builtins for operations like
bfrev, but NIR can recognize the construct and optimize it to
bitfield_reverse, which pre-nvc0 would then fail to codegen.  Prevents a
regression when moving to nir-to-tgsi.  Other lower_bitfield flags are set
as well for when someone comes along and adds optimizations for them too.

Reviewed-by: Timothy Arceri <tarceri at itsqueeze.com>
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 603c36c1f1d..40f02cfc028 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -3257,14 +3257,14 @@ nvir_nir_shader_compiler_options(int chipset)
    op.lower_sincos = false;
    op.lower_fmod = true;
    op.lower_bitfield_extract = false;
-   op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
+   op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHIPSET);
    op.lower_bitfield_insert = false;
-   op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
+   op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHIPSET);
    op.lower_bitfield_insert_to_bitfield_select = false;
-   op.lower_bitfield_reverse = false;
-   op.lower_bit_count = false;
-   op.lower_ifind_msb = false;
-   op.lower_find_lsb = false;
+   op.lower_bitfield_reverse = (chipset < NVISA_GF100_CHIPSET);
+   op.lower_bit_count = (chipset < NVISA_GF100_CHIPSET);
+   op.lower_ifind_msb = (chipset < NVISA_GF100_CHIPSET);
+   op.lower_find_lsb = (chipset < NVISA_GF100_CHIPSET);
    op.lower_uadd_carry = true; // TODO
    op.lower_usub_borrow = true; // TODO
    op.lower_mul_high = false;