Mesa (staging/22.0): intel: fix URB programming for GT1s

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: a28934a0ab6e346c8561067fc153db62305edd94
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a28934a0ab6e346c8561067fc153db62305edd94

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Sat Mar 26 23:59:26 2022 +0200

intel: fix URB programming for GT1s

We're missing a programming restriction.

Hopefully fixing
dEQP-VK.spirv_assembly.instruction.graphics.float16.arithmetic_1.* on
Gfx9atoms

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6216
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>.
Tested-by: Mark Janes <markjanes at swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15596>
(cherry picked from commit b07c215c353fbbf12f9a1cb154f0a46b52451b6a)

---

 .pick_status.json                   |  2 +-
 src/intel/common/intel_urb_config.c | 29 +++++++++++++++++++++++------
 2 files changed, 24 insertions(+), 7 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index acc06e56746..f2ce60b3b1b 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1532,7 +1532,7 @@
         "description": "intel: fix URB programming for GT1s",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "because_sha": null
     },
     {
diff --git a/src/intel/common/intel_urb_config.c b/src/intel/common/intel_urb_config.c
index 52551d02403..2f7d72cc31f 100644
--- a/src/intel/common/intel_urb_config.c
+++ b/src/intel/common/intel_urb_config.c
@@ -225,14 +225,32 @@ intel_get_urb_config(const struct intel_device_info *devinfo,
    }
 
    /* Lay out the URB in pipeline order: push constants, VS, HS, DS, GS. */
-   int next = push_constant_chunks;
+   int first_urb = push_constant_chunks;
+
+   /* From the BDW PRM: for 3DSTATE_URB_*: VS URB Starting Address
+    *
+    *    "Value: [4,48] Device [SliceCount] GT 1"
+    *
+    * From the ICL PRMs and above :
+    *
+    *    "If CTXT_SR_CTL::POSH_Enable is clear and Push Constants are required
+    *     or Device[SliceCount] GT 1, the lower limit is 4."
+    *
+    *    "If Push Constants are not required andDevice[SliceCount] == 1, the
+    *     lower limit is 0."
+    */
+   if ((devinfo->ver == 8 && devinfo->num_slices == 1) ||
+       (devinfo->ver >= 11 && push_constant_chunks > 0 && devinfo->num_slices == 1))
+      first_urb = MAX2(first_urb, 4);
+
+   int next_urb = first_urb;
    for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
       if (entries[i]) {
-         start[i] = next;
-         next += chunks[i];
+         start[i] = next_urb;
+         next_urb += chunks[i];
       } else {
-         /* Just put disabled stages at the beginning. */
-         start[i] = 0;
+         /* Put disabled stages at the beginning of the valid range */
+         start[i] = first_urb;
       }
    }
 
@@ -359,4 +377,3 @@ intel_get_mesh_urb_config(const struct intel_device_info *devinfo,
 
    return r;
 }
-