Mesa (main): dzn: Update the draw_id sysval when issuing indirect draws

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Module: Mesa
Branch: main
Commit: 2eadd8dd16a12f545f80b943100be2350da83e2e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eadd8dd16a12f545f80b943100be2350da83e2e

Author: Boris Brezillon <boris.brezillon at collabora.com>
Date:   Wed Apr  6 18:23:37 2022 +0200

dzn: Update the draw_id sysval when issuing indirect draws

Reviewed-by: Jesse Natalie <jenatali at microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15912>

---

 src/microsoft/vulkan/dzn_nir.c      | 32 +++++++++++++++++---------------
 src/microsoft/vulkan/dzn_nir.h      |  2 ++
 src/microsoft/vulkan/dzn_pipeline.c | 11 ++++++++++-
 3 files changed, 29 insertions(+), 16 deletions(-)

diff --git a/src/microsoft/vulkan/dzn_nir.c b/src/microsoft/vulkan/dzn_nir.c
index f8f5ce056eb..146322756a1 100644
--- a/src/microsoft/vulkan/dzn_nir.c
+++ b/src/microsoft/vulkan/dzn_nir.c
@@ -151,20 +151,21 @@ dzn_nir_indirect_draw_shader(enum dzn_indirect_draw_type type)
    nir_ssa_def *base_instance =
       indexed ? draw_info2 : nir_channel(&b, draw_info1, 3);
 
-   nir_ssa_def *exec_vals[7] = {
+   nir_ssa_def *exec_vals[8] = {
       first_vertex,
       base_instance,
+      index,
    };
 
    if (triangle_fan) {
       /* Patch {vertex,index}_count and first_index */
       nir_ssa_def *triangle_count =
          nir_usub_sat(&b, nir_channel(&b, draw_info1, 0), nir_imm_int(&b, 2));
-      exec_vals[2] = nir_imul_imm(&b, triangle_count, 3);
-      exec_vals[3] = nir_channel(&b, draw_info1, 1);
-      exec_vals[4] = nir_imm_int(&b, 0);
-      exec_vals[5] = first_vertex;
-      exec_vals[6] = base_instance;
+      exec_vals[3] = nir_imul_imm(&b, triangle_count, 3);
+      exec_vals[4] = nir_channel(&b, draw_info1, 1);
+      exec_vals[5] = nir_imm_int(&b, 0);
+      exec_vals[6] = first_vertex;
+      exec_vals[7] = base_instance;
 
       nir_ssa_def *triangle_fan_exec_buf_desc =
          dzn_nir_create_bo_desc(&b, nir_var_mem_ssbo, 0, 3,
@@ -174,6 +175,7 @@ dzn_nir_indirect_draw_shader(enum dzn_indirect_draw_type type)
       nir_ssa_def *triangle_fan_index_buf_addr_lo =
          nir_iadd(&b, nir_channel(&b, params, 2),
                   nir_imul(&b, triangle_fan_index_buf_stride, index));
+
       nir_ssa_def *addr_lo_overflow =
          nir_ult(&b, triangle_fan_index_buf_addr_lo, nir_channel(&b, params, 2));
       nir_ssa_def *triangle_fan_index_buf_addr_hi =
@@ -213,22 +215,22 @@ dzn_nir_indirect_draw_shader(enum dzn_indirect_draw_type type)
 
       nir_store_ssbo(&b, nir_vec(&b, ibview_vals, ARRAY_SIZE(ibview_vals)),
                      exec_buf_desc, exec_offset,
-                     .write_mask = 0x3, .access = ACCESS_NON_READABLE, .align_mul = 4);
+                     .write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 16);
       exec_offset = nir_iadd_imm(&b, exec_offset, ARRAY_SIZE(ibview_vals) * 4);
    } else {
-      exec_vals[2] = nir_channel(&b, draw_info1, 0);
-      exec_vals[3] = nir_channel(&b, draw_info1, 1);
-      exec_vals[4] = nir_channel(&b, draw_info1, 2);
-      exec_vals[5] = nir_channel(&b, draw_info1, 3);
-      exec_vals[6] = draw_info2;
+      exec_vals[3] = nir_channel(&b, draw_info1, 0);
+      exec_vals[4] = nir_channel(&b, draw_info1, 1);
+      exec_vals[5] = nir_channel(&b, draw_info1, 2);
+      exec_vals[6] = nir_channel(&b, draw_info1, 3);
+      exec_vals[7] = draw_info2;
    }
 
    nir_store_ssbo(&b, nir_vec(&b, exec_vals, 4),
                   exec_buf_desc, exec_offset,
-                  .write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 4);
-   nir_store_ssbo(&b, nir_vec(&b, &exec_vals[4], 3),
+                  .write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 16);
+   nir_store_ssbo(&b, nir_vec(&b, &exec_vals[4], 4),
                   exec_buf_desc, nir_iadd_imm(&b, exec_offset, 16),
-                  .write_mask = 7, .access = ACCESS_NON_READABLE, .align_mul = 4);
+                  .write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 16);
 
 
    return b.shader;
diff --git a/src/microsoft/vulkan/dzn_nir.h b/src/microsoft/vulkan/dzn_nir.h
index 4b3fef49ff7..d05f1ba5030 100644
--- a/src/microsoft/vulkan/dzn_nir.h
+++ b/src/microsoft/vulkan/dzn_nir.h
@@ -59,6 +59,7 @@ struct dzn_indirect_draw_exec_params {
    struct {
       uint32_t first_vertex;
       uint32_t base_instance;
+      uint32_t draw_id;
    } sysvals;
    union {
       struct dzn_indirect_draw_params draw;
@@ -71,6 +72,7 @@ struct dzn_indirect_triangle_fan_draw_exec_params {
    struct {
       uint32_t first_vertex;
       uint32_t base_instance;
+      uint32_t draw_id;
    } sysvals;
    union {
       struct dzn_indirect_draw_params draw;
diff --git a/src/microsoft/vulkan/dzn_pipeline.c b/src/microsoft/vulkan/dzn_pipeline.c
index 9fc175e34f7..403f41971f5 100644
--- a/src/microsoft/vulkan/dzn_pipeline.c
+++ b/src/microsoft/vulkan/dzn_pipeline.c
@@ -948,7 +948,7 @@ out:
    return ret;
 }
 
-#define DZN_INDIRECT_CMD_SIG_MAX_ARGS 3
+#define DZN_INDIRECT_CMD_SIG_MAX_ARGS 4
 
 ID3D12CommandSignature *
 dzn_graphics_pipeline_get_indirect_cmd_sig(struct dzn_graphics_pipeline *pipeline,
@@ -984,6 +984,15 @@ dzn_graphics_pipeline_get_indirect_cmd_sig(struct dzn_graphics_pipeline *pipelin
       },
    };
 
+   cmd_args[cmd_arg_count++] = (D3D12_INDIRECT_ARGUMENT_DESC) {
+      .Type = D3D12_INDIRECT_ARGUMENT_TYPE_CONSTANT,
+      .Constant = {
+         .RootParameterIndex = pipeline->base.root.sysval_cbv_param_idx,
+         .DestOffsetIn32BitValues = offsetof(struct dxil_spirv_vertex_runtime_data, draw_id) / 4,
+         .Num32BitValuesToSet = 1,
+      },
+   };
+
    cmd_args[cmd_arg_count++] = (D3D12_INDIRECT_ARGUMENT_DESC) {
       .Type = indexed ?
               D3D12_INDIRECT_ARGUMENT_TYPE_DRAW_INDEXED :