Mesa (main): radeonsi: add an SQTT workaround for chips with disabled RBs
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Fri Apr 22 21:24:18 UTC 2022
Module: Mesa
Branch: main
Commit: 91bc463a51f77acba3ed4dbe30c6a56bd80a9a2b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=91bc463a51f77acba3ed4dbe30c6a56bd80a9a2b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Mar 22 02:11:16 2022 -0400
radeonsi: add an SQTT workaround for chips with disabled RBs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15965>
---
src/amd/common/ac_gpu_info.c | 8 ++++++++
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/drivers/radeonsi/si_sqtt.c | 26 ++++++++++++++++++--------
3 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index a327766c9c5..d0a0403657b 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -1248,6 +1248,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->has_3d_cube_border_color_mipmap = info->has_graphics || info->family == CHIP_ARCTURUS;
info->never_stop_sq_perf_counters = info->chip_class == GFX10 ||
info->chip_class == GFX10_3;
+ info->has_sqtt_rb_harvest_bug = (info->family == CHIP_DIMGREY_CAVEFISH ||
+ info->family == CHIP_BEIGE_GOBY ||
+ info->family == CHIP_YELLOW_CARP ||
+ info->family == CHIP_VANGOGH) &&
+ util_bitcount(info->enabled_rb_mask) !=
+ info->max_render_backends;
+
info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
if (!info->has_graphics && info->family >= CHIP_ALDEBARAN) {
@@ -1361,6 +1368,7 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
fprintf(f, " has_32bit_predication = %i\n", info->has_32bit_predication);
fprintf(f, " has_3d_cube_border_color_mipmap = %i\n", info->has_3d_cube_border_color_mipmap);
fprintf(f, " never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters);
+ fprintf(f, " has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug);
fprintf(f, "Display features:\n");
fprintf(f, " use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index ea6a80a4d41..e8dd0d8504a 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -88,6 +88,7 @@ struct radeon_info {
bool has_32bit_predication;
bool has_3d_cube_border_color_mipmap;
bool never_stop_sq_perf_counters;
+ bool has_sqtt_rb_harvest_bug;
/* Display features. */
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c
index 8a0a39eb24f..bb351f9b057 100644
--- a/src/gallium/drivers/radeonsi/si_sqtt.c
+++ b/src/gallium/drivers/radeonsi/si_sqtt.c
@@ -303,6 +303,14 @@ si_emit_thread_trace_stop(struct si_context *sctx,
radeon_emit(EVENT_TYPE(V_028A90_THREAD_TRACE_FINISH) | EVENT_INDEX(0));
radeon_end();
+ if (sctx->screen->info.has_sqtt_rb_harvest_bug) {
+ /* Some chips with disabled RBs should wait for idle because FINISH_DONE doesn't work. */
+ sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
+ SI_CONTEXT_FLUSH_AND_INV_DB |
+ SI_CONTEXT_CS_PARTIAL_FLUSH;
+ sctx->emit_cache_flush(sctx, cs);
+ }
+
for (unsigned se = 0; se < max_se; se++) {
if (si_se_is_disabled(sctx, se))
continue;
@@ -316,14 +324,16 @@ si_emit_thread_trace_stop(struct si_context *sctx,
S_030800_INSTANCE_BROADCAST_WRITES(1));
if (sctx->chip_class >= GFX10) {
- /* Make sure to wait for the trace buffer. */
- radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0));
- radeon_emit(WAIT_REG_MEM_NOT_EQUAL); /* wait until the register is equal to the reference value */
- radeon_emit(R_008D20_SQ_THREAD_TRACE_STATUS >> 2); /* register */
- radeon_emit(0);
- radeon_emit(0); /* reference value */
- radeon_emit(~C_008D20_FINISH_DONE); /* mask */
- radeon_emit(4); /* poll interval */
+ if (!sctx->screen->info.has_sqtt_rb_harvest_bug) {
+ /* Make sure to wait for the trace buffer. */
+ radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0));
+ radeon_emit(WAIT_REG_MEM_NOT_EQUAL); /* wait until the register is equal to the reference value */
+ radeon_emit(R_008D20_SQ_THREAD_TRACE_STATUS >> 2); /* register */
+ radeon_emit(0);
+ radeon_emit(0); /* reference value */
+ radeon_emit(~C_008D20_FINISH_DONE); /* mask */
+ radeon_emit(4); /* poll interval */
+ }
/* Disable the thread trace mode. */
radeon_set_privileged_config_reg(R_008D1C_SQ_THREAD_TRACE_CTRL,
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