Mesa (main): svga: Add support for SVGAv3

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Module: Mesa
Branch: main
Commit: 16019ff7ccfca0ffa710912b20e195bd7a4eae29
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=16019ff7ccfca0ffa710912b20e195bd7a4eae29

Author: Zack Rusin <zackr at vmware.com>
Date:   Tue Feb  8 16:41:32 2022 -0500

svga: Add support for SVGAv3

SVGAv3 changes the PCI id due to differences in how PCI configuration
is handled - removal of VRAM and FIFO PCI resources, switch to MMIO
registers and MSI/MSI-X IRQ support but the 3D commands remain largely
the same.

This enables 3D/graphics acceleration support on SVGAv3.

Signed-off-by: Zack Rusin <zackr at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16061>

---

 include/pci_ids/vmwgfx_pci_ids.h               |  1 +
 src/gallium/drivers/svga/svga_screen.c         |  6 +++++-
 src/gallium/drivers/svga/svga_winsys.h         |  3 +++
 src/gallium/winsys/svga/drm/vmw_screen_ioctl.c | 10 ++++++++++
 src/gallium/winsys/svga/drm/vmwgfx_drm.h       |  9 ++++++++-
 5 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/include/pci_ids/vmwgfx_pci_ids.h b/include/pci_ids/vmwgfx_pci_ids.h
index 124d75b7253..6d809ea9c6c 100644
--- a/include/pci_ids/vmwgfx_pci_ids.h
+++ b/include/pci_ids/vmwgfx_pci_ids.h
@@ -1 +1,2 @@
 CHIPSET(0x0405, SVGAII, SVGAII)
+CHIPSET(0x0406, SVGAv3, SVGAv3)
diff --git a/src/gallium/drivers/svga/svga_screen.c b/src/gallium/drivers/svga/svga_screen.c
index 44ab599f60e..93f98976bd7 100644
--- a/src/gallium/drivers/svga/svga_screen.c
+++ b/src/gallium/drivers/svga/svga_screen.c
@@ -432,7 +432,11 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_VENDOR_ID:
       return 0x15ad; /* VMware Inc. */
    case PIPE_CAP_DEVICE_ID:
-      return 0x0405; /* assume SVGA II */
+      if (sws->device_id) {
+         return sws->device_id;
+      } else {
+         return 0x0405; /* assume SVGA II */
+      }
    case PIPE_CAP_ACCELERATED:
       return 0; /* XXX: */
    case PIPE_CAP_VIDEO_MEMORY:
diff --git a/src/gallium/drivers/svga/svga_winsys.h b/src/gallium/drivers/svga/svga_winsys.h
index 7e05b811e3a..6818c293174 100644
--- a/src/gallium/drivers/svga/svga_winsys.h
+++ b/src/gallium/drivers/svga/svga_winsys.h
@@ -824,6 +824,9 @@ struct svga_winsys_screen
 
    /** Have GL43 capable device */
    boolean have_gl43;
+
+   /** SVGA device_id version we're running on */
+   uint16_t device_id;
 };
 
 
diff --git a/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c b/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c
index 3e952a96778..7b83cbce26d 100644
--- a/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c
+++ b/src/gallium/winsys/svga/drm/vmw_screen_ioctl.c
@@ -1053,6 +1053,16 @@ vmw_ioctl_init(struct vmw_winsys_screen *vws)
    vws->base.have_sm4_1 = FALSE;
    vws->base.have_intra_surface_copy = FALSE;
 
+   memset(&gp_arg, 0, sizeof(gp_arg));
+   gp_arg.param = DRM_VMW_PARAM_DEVICE_ID;
+   ret = drmCommandWriteRead(vws->ioctl.drm_fd, DRM_VMW_GET_PARAM,
+              &gp_arg, sizeof(gp_arg));
+   if (ret || gp_arg.value == 0) {
+      vws->base.device_id = 0x0405; /* assume SVGA II */
+   } else {
+      vws->base.device_id = gp_arg.value;
+   }
+
    if (vws->base.have_gb_objects) {
       memset(&gp_arg, 0, sizeof(gp_arg));
       gp_arg.param = DRM_VMW_PARAM_MAX_MOB_MEMORY;
diff --git a/src/gallium/winsys/svga/drm/vmwgfx_drm.h b/src/gallium/winsys/svga/drm/vmwgfx_drm.h
index 05763d834fb..26549c86a91 100644
--- a/src/gallium/winsys/svga/drm/vmwgfx_drm.h
+++ b/src/gallium/winsys/svga/drm/vmwgfx_drm.h
@@ -1,6 +1,6 @@
 /**************************************************************************
  *
- * Copyright © 2009-2021 VMware, Inc., Palo Alto, CA., USA
+ * Copyright © 2009-2022 VMware, Inc., Palo Alto, CA., USA
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -92,6 +92,12 @@ extern "C" {
  *
  * DRM_VMW_PARAM_SM5
  * SM5 support is enabled.
+ *
+ * DRM_VMW_PARAM_GL43
+ * SM5.1+GL4.3 support is enabled.
+ *
+ * DRM_VMW_PARAM_DEVICE_ID
+ * PCI ID of the underlying SVGA device.
  */
 
 #define DRM_VMW_PARAM_NUM_STREAMS      0
@@ -111,6 +117,7 @@ extern "C" {
 #define DRM_VMW_PARAM_SM4_1            14
 #define DRM_VMW_PARAM_SM5              15
 #define DRM_VMW_PARAM_GL43             16
+#define DRM_VMW_PARAM_DEVICE_ID        17
 
 /**
  * enum drm_vmw_handle_type - handle type for ref ioctls