Mesa (main): r600: tune nir options

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: a8430c43a7289f94c59146dce605cc2507062124
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8430c43a7289f94c59146dce605cc2507062124

Author: Gert Wollny <gert.wollny at collabora.com>
Date:   Sun Apr 24 14:25:45 2022 +0200

r600: tune nir options

* Don't lower fp64 to software when on Cayman but
* lower fpow only when on native NIR, the TGSI backend handles
  TGSI_OPCODE_POW

Fixes: a4840e15ab77b44a72cabd7d503172e8357477eb
  r600: Use nir-to-tgsi instead of TGSI when the NIR debug opt is disabled.

Signed-off-by: Gert Wollny <gert.wollny at collabora.com>
Reviewed-by: Emma Anholt <emma at anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16130>

---

 src/gallium/drivers/r600/r600_pipe_common.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe_common.c b/src/gallium/drivers/r600/r600_pipe_common.c
index 4e3a384422b..acb5551c8d6 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.c
+++ b/src/gallium/drivers/r600/r600_pipe_common.c
@@ -1330,13 +1330,10 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
 		.fuse_ffma64 = true,
 		.lower_flrp32 = true,
 		.lower_flrp64 = true,
-		.lower_fpow = true,
 		.lower_fdiv = true,
 		.lower_isign = true,
 		.lower_fsign = true,
 		.lower_fmod = true,
-		.lower_doubles_options = nir_lower_fp64_full_software,
-		.lower_int64_options = ~0,
 		.lower_extract_byte = true,
 		.lower_extract_word = true,
 		.lower_insert_byte = true,
@@ -1362,12 +1359,31 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
 
 	rscreen->nir_options = nir_options;
 
+        /* The TGSI code path handles OPCODE_POW, but has problems with the
+         * lowered version, the NIT code path does the rightthing with the
+         * lowered code */
+        rscreen->nir_options.lower_fpow = rscreen->debug_flags & DBG_NIR_PREFERRED;
+
 	if (rscreen->info.chip_class < EVERGREEN) {
 		/* Pre-EG doesn't have these ALU ops */
 		rscreen->nir_options.lower_bit_count = true;
 		rscreen->nir_options.lower_bitfield_reverse = true;
 	}
 
+        if (rscreen->info.chip_class < CAYMAN) {
+           rscreen->nir_options.lower_doubles_options = nir_lower_fp64_full_software;
+           rscreen->nir_options.lower_int64_options = ~0;
+        } else {
+           rscreen->nir_options.lower_doubles_options =
+                 nir_lower_ddiv |
+                 nir_lower_dfloor |
+                 nir_lower_dceil |
+                 nir_lower_dmod |
+                 nir_lower_dsub |
+                 nir_lower_dtrunc;
+           rscreen->nir_options.lower_int64_options = ~0;
+        }
+
 	if (!(rscreen->debug_flags & DBG_NIR_PREFERRED)) {
 		/* TGSI is vector, and NIR-to-TGSI doesn't like it when the
 		 * input vars have been scalarized.