Mesa (main): isl,iris: Add DG2 CCS modifier support for XeHP
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Thu Apr 28 20:39:43 UTC 2022
Module: Mesa
Branch: main
Commit: b023f18badf34e8f11654af620b477d028e866be
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b023f18badf34e8f11654af620b477d028e866be
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Apr 29 12:04:04 2021 -0700
isl,iris: Add DG2 CCS modifier support for XeHP
Cc: 22.1 <mesa-stable>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14521>
---
src/gallium/drivers/iris/iris_resource.c | 48 +++++++++++++++++++++++++++++++-
src/intel/isl/isl_drm.c | 21 ++++++++++++++
2 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 81d757edcf8..4742a996a2c 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -63,6 +63,8 @@ enum modifier_priority {
MODIFIER_PRIORITY_Y_GFX12_RC_CCS,
MODIFIER_PRIORITY_Y_GFX12_RC_CCS_CC,
MODIFIER_PRIORITY_4,
+ MODIFIER_PRIORITY_4_DG2_RC_CCS,
+ MODIFIER_PRIORITY_4_DG2_RC_CCS_CC,
};
static const uint64_t priority_to_modifier[] = {
@@ -74,6 +76,8 @@ static const uint64_t priority_to_modifier[] = {
[MODIFIER_PRIORITY_Y_GFX12_RC_CCS] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
[MODIFIER_PRIORITY_Y_GFX12_RC_CCS_CC] = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
[MODIFIER_PRIORITY_4] = I915_FORMAT_MOD_4_TILED,
+ [MODIFIER_PRIORITY_4_DG2_RC_CCS] = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
+ [MODIFIER_PRIORITY_4_DG2_RC_CCS_CC] = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
};
static bool
@@ -103,6 +107,9 @@ modifier_is_supported(const struct intel_device_info *devinfo,
return false;
break;
case I915_FORMAT_MOD_4_TILED:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
if (devinfo->verx10 < 125)
return false;
break;
@@ -113,6 +120,7 @@ modifier_is_supported(const struct intel_device_info *devinfo,
/* Check remaining requirements. */
switch (modifier) {
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (INTEL_DEBUG(DEBUG_NO_CCS))
return false;
@@ -130,6 +138,8 @@ modifier_is_supported(const struct intel_device_info *devinfo,
return false;
}
break;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_CCS: {
@@ -166,6 +176,12 @@ select_best_modifier(struct intel_device_info *devinfo,
continue;
switch (modifiers[i]) {
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ prio = MAX2(prio, MODIFIER_PRIORITY_4_DG2_RC_CCS_CC);
+ break;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ prio = MAX2(prio, MODIFIER_PRIORITY_4_DG2_RC_CCS);
+ break;
case I915_FORMAT_MOD_4_TILED:
prio = MAX2(prio, MODIFIER_PRIORITY_4);
break;
@@ -206,7 +222,7 @@ static inline bool is_modifier_external_only(enum pipe_format pfmt,
* of media-compressed surfaces, resolves are avoided.
*/
return util_format_is_yuv(pfmt) ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+ isl_drm_modifier_get_info(modifier)->aux_usage == ISL_AUX_USAGE_MC;
}
static void
@@ -224,6 +240,9 @@ iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
DRM_FORMAT_MOD_LINEAR,
I915_FORMAT_MOD_X_TILED,
I915_FORMAT_MOD_4_TILED,
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
+ I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
+ I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
I915_FORMAT_MOD_Y_TILED,
I915_FORMAT_MOD_Y_TILED_CCS,
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
@@ -280,10 +299,13 @@ iris_get_dmabuf_modifier_planes(struct pipe_screen *pscreen, uint64_t modifier,
switch (modifier) {
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
return 3;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_CCS:
return 2 * planes;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
default:
return planes;
}
@@ -977,6 +999,14 @@ iris_resource_finish_aux_import(struct pipe_screen *pscreen,
4096, IRIS_MEMZONE_OTHER, BO_ALLOC_ZEROED);
}
break;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ assert(num_main_planes == 1);
+ assert(num_planes == 1);
+ res->aux.clear_color_bo =
+ iris_bo_alloc(screen->bufmgr, "clear color_buffer",
+ iris_get_aux_clear_color_state_size(screen, res),
+ 4096, IRIS_MEMZONE_OTHER, BO_ALLOC_ZEROED);
+ break;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
assert(num_main_planes == 1 && num_planes == 3);
import_aux_info(r[0], r[1]);
@@ -988,6 +1018,16 @@ iris_resource_finish_aux_import(struct pipe_screen *pscreen,
r[0]->aux.clear_color_offset = r[2]->aux.clear_color_offset;
r[0]->aux.clear_color_unknown = true;
break;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ assert(num_main_planes == 1);
+ assert(num_planes == 2);
+
+ /* Import the clear color BO. */
+ iris_bo_reference(r[1]->aux.clear_color_bo);
+ r[0]->aux.clear_color_bo = r[1]->aux.clear_color_bo;
+ r[0]->aux.clear_color_offset = r[1]->aux.clear_color_offset;
+ r[0]->aux.clear_color_unknown = true;
+ break;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (num_main_planes == 1 && num_planes == 2) {
import_aux_info(r[0], r[1]);
@@ -1001,6 +1041,9 @@ iris_resource_finish_aux_import(struct pipe_screen *pscreen,
}
assert(!isl_aux_usage_has_fast_clears(res->mod_info->aux_usage));
break;
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ assert(!isl_aux_usage_has_fast_clears(res->mod_info->aux_usage));
+ break;
default:
assert(res->mod_info->aux_usage == ISL_AUX_USAGE_NONE);
break;
@@ -1247,6 +1290,9 @@ mod_plane_is_clear_color(uint64_t modifier, uint32_t plane)
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
assert(mod_info->supports_clear_color);
return plane == 2;
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ assert(mod_info->supports_clear_color);
+ return plane == 1;
default:
assert(!mod_info->supports_clear_color);
return false;
diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c
index 616ae4b8bb5..c42bdfdc33c 100644
--- a/src/intel/isl/isl_drm.c
+++ b/src/intel/isl/isl_drm.c
@@ -126,6 +126,27 @@ isl_drm_modifier_info_list[] = {
.name = "I915_FORMAT_MOD_4_TILED",
.tiling = ISL_TILING_4,
},
+ {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
+ .name = "I915_FORMAT_MOD_4_TILED_DG2_RC_CCS",
+ .tiling = ISL_TILING_4,
+ .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E,
+ .supports_clear_color = false,
+ },
+ {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
+ .name = "I915_FORMAT_MOD_4_TILED_DG2_MC_CCS",
+ .tiling = ISL_TILING_4,
+ .aux_usage = ISL_AUX_USAGE_MC,
+ .supports_clear_color = false,
+ },
+ {
+ .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
+ .name = "I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC",
+ .tiling = ISL_TILING_4,
+ .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E,
+ .supports_clear_color = true,
+ },
{
.modifier = DRM_FORMAT_MOD_INVALID,
},
More information about the mesa-commit
mailing list