Mesa (main): radeonsi: drop assume_no_z_fights option
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Fri Apr 29 08:20:49 UTC 2022
Module: Mesa
Branch: main
Commit: f59c8c6e1c4838213b76582a7204e6a889990aa9
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f59c8c6e1c4838213b76582a7204e6a889990aa9
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Wed Mar 16 10:40:00 2022 +0100
radeonsi: drop assume_no_z_fights option
And garbage collect the code that was only used by this option.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16139>
---
src/gallium/drivers/radeonsi/driinfo_radeonsi.h | 1 -
src/gallium/drivers/radeonsi/si_pipe.c | 2 --
src/gallium/drivers/radeonsi/si_pipe.h | 1 -
src/gallium/drivers/radeonsi/si_state.c | 16 +++-------------
src/gallium/drivers/radeonsi/si_state.h | 5 -----
src/util/driconf.h | 4 ----
6 files changed, 3 insertions(+), 26 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index 20837675477..847c87900c2 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,7 +1,6 @@
// DriConf options specific to radeonsi
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_ADAPTIVE_SYNC(true)
-DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS(false)
DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS(false)
DRI_CONF_SECTION_END
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 0f8d5b74a84..6456b29cbd4 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1267,8 +1267,6 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
sscreen->has_out_of_order_rast =
sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
- sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights") ||
- driQueryOptionb(config->options, "allow_draw_out_of_order");
sscreen->allow_draw_out_of_order = driQueryOptionb(config->options, "allow_draw_out_of_order");
sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) &&
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 70599622533..577b29a3c5e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -566,7 +566,6 @@ struct si_screen {
unsigned pbb_persistent_states_per_bin;
bool has_draw_indirect_multi;
bool has_out_of_order_rast;
- bool assume_no_z_fights;
bool allow_draw_out_of_order;
bool dpbb_allowed;
bool use_ngg;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index dc2c82aaf8b..c805e8819d7 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1284,7 +1284,6 @@ static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *st
static void *si_create_dsa_state(struct pipe_context *ctx,
const struct pipe_depth_stencil_alpha_state *state)
{
- struct si_context *sctx = (struct si_context *)ctx;
struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
struct si_pm4_state *pm4 = &dsa->pm4;
unsigned db_depth_control;
@@ -1373,12 +1372,6 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
!dsa->depth_write_enabled ||
(state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER);
- dsa->order_invariance[1].pass_last = sctx->screen->assume_no_z_fights &&
- !dsa->stencil_write_enabled && dsa->depth_write_enabled &&
- zfunc_is_ordered;
- dsa->order_invariance[0].pass_last =
- sctx->screen->assume_no_z_fights && dsa->depth_write_enabled && zfunc_is_ordered;
-
return dsa;
}
@@ -3528,8 +3521,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
return false;
struct si_dsa_order_invariance dsa_order_invariant = {.zs = true,
- .pass_set = true,
- .pass_last = false};
+ .pass_set = true};
if (sctx->framebuffer.state.zsbuf) {
struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
@@ -3563,10 +3555,8 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
return false;
}
- if (colormask & ~blendmask) {
- if (!dsa_order_invariant.pass_last)
- return false;
- }
+ if (colormask & ~blendmask)
+ return false;
return true;
}
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 3298db4b454..4cf01badc14 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -116,11 +116,6 @@ struct si_dsa_order_invariance {
* guaranteed to be invariant under changes to the order in which
* fragments arrive. */
bool pass_set : 1;
-
- /** Whether the last fragment that passes the combined Z/S test at each
- * sample is guaranteed to be invariant under changes to the order in
- * which fragments arrive. */
- bool pass_last : 1;
};
struct si_state_dsa {
diff --git a/src/util/driconf.h b/src/util/driconf.h
index c4eb8b33bd1..a5ca3f1d6c7 100644
--- a/src/util/driconf.h
+++ b/src/util/driconf.h
@@ -472,10 +472,6 @@
* \brief radeonsi specific configuration options
*/
-#define DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS(def) \
- DRI_CONF_OPT_B(radeonsi_assume_no_z_fights, def, \
- "Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)")
-
#define DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS(def) \
DRI_CONF_OPT_B(radeonsi_zerovram, def, \
"Zero all vram allocations")
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