Mesa (staging/21.3): intel/fs: don't set allow_sample_mask for CS intrinsics

[GitLab Mirror]

Module: Mesa
Branch: staging/21.3
Commit: 4bf9a88a62515031c9de6bb5ee48a56495ec89a7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bf9a88a62515031c9de6bb5ee48a56495ec89a7

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Thu Feb  3 11:33:26 2022 +0200

intel/fs: don't set allow_sample_mask for CS intrinsics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 77486db867bd ("intel/fs: Disable sample mask predication for scratch stores")
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13719>
(cherry picked from commit c89024e4463389663cf7f7d2f2752de2029efb23)

---

 .pick_status.json                 | 2 +-
 src/intel/compiler/brw_fs_nir.cpp | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index ca83a705ce3..8fb5cfe731b 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -283,7 +283,7 @@
         "description": "intel/fs: don't set allow_sample_mask for CS intrinsics",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "77486db867bd39aa9b76e549c946b0a165fcb21a"
     },
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 7e48e213e8d..9376537bd44 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3928,7 +3928,10 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
       srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM);
       srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
       srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
-      srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(1);
+      /* No point in masking with sample mask, here we're handling compute
+       * intrinsics.
+       */
+      srcs[SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK] = brw_imm_ud(0);
 
       fs_reg data = get_nir_src(instr->src[0]);
       data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);