Mesa (staging/22.0): intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: 826f071e2daa86b7cbec8d1e2b827bc80ecb033f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=826f071e2daa86b7cbec8d1e2b827bc80ecb033f

Author: Tapani Pälli <tapani.palli at intel.com>
Date:   Mon Jan 31 11:48:49 2022 +0200

intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 442628b70244f2c9fd0ed79e0656e999ee6fffca)

---

 .pick_status.json           | 2 +-
 src/intel/genxml/gen12.xml  | 1 +
 src/intel/genxml/gen125.xml | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 14df5d67c65..7a6082602a4 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -76,7 +76,7 @@
         "description": "intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 08a49c33abf..c250da0c07c 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -6450,6 +6450,7 @@
   <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
     <field name="DWord Length" start="0" end="7" type="uint" default="4"/>
     <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
+    <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/>
     <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
     <field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
     <field name="Command SubType" start="27" end="28" type="uint" default="3"/>
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 6f2def17848..a11b70b405e 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -6781,6 +6781,7 @@
   <instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
     <field name="DWord Length" start="0" end="7" type="uint" default="4"/>
     <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
+    <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool"/>
     <field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool"/>
     <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
     <field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>