Mesa (main): radeonsi: add SI_PROFILE_CLAMP_DIV_BY_ZERO
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Wed Feb 16 12:10:52 UTC 2022
Module: Mesa
Branch: main
Commit: 9685b5785b0a3862fb3eb28cd8f5ffc1a1ccf984
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9685b5785b0a3862fb3eb28cd8f5ffc1a1ccf984
Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date: Mon Feb 7 18:45:50 2022 +0100
radeonsi: add SI_PROFILE_CLAMP_DIV_BY_ZERO
To enable divide by zero clamping per shader, instead of per app.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14931>
---
src/gallium/drivers/radeonsi/si_shader.h | 1 +
src/gallium/drivers/radeonsi/si_shader_llvm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index 62283444f25..24f2e829ed6 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -293,6 +293,7 @@ enum
#define SI_PROFILE_IGNORE_LLVM_DISCARD_BUG (1 << 2)
#define SI_PROFILE_VS_NO_BINNING (1 << 3)
#define SI_PROFILE_PS_NO_BINNING (1 << 4)
+#define SI_PROFILE_CLAMP_DIV_BY_ZERO (1 << 5)
/**
* For VS shader keys, describe any fixups required for vertex fetch.
diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c
index c6161858c1f..400d1b2230f 100644
--- a/src/gallium/drivers/radeonsi/si_shader_llvm.c
+++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c
@@ -519,7 +519,6 @@ static bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *
ctx->abi.clamp_shadow_reference = true;
ctx->abi.robust_buffer_access = true;
ctx->abi.convert_undef_to_zero = true;
- ctx->abi.clamp_div_by_zero = ctx->screen->options.clamp_div_by_zero;
ctx->abi.adjust_frag_coord_z = false;
ctx->abi.disable_aniso_single_level = true;
@@ -536,6 +535,9 @@ static bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *
ctx->abi.outputs[i * 4 + j] = ac_build_alloca_undef(&ctx->ac, type, "");
}
+ ctx->abi.clamp_div_by_zero = ctx->screen->options.clamp_div_by_zero ||
+ info->options & SI_PROFILE_CLAMP_DIV_BY_ZERO;
+
ac_nir_translate(&ctx->ac, &ctx->abi, &ctx->args, nir);
return true;
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