Mesa (main): radv: Don't disturb dynamic primitive topology with mesh shading.

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Module: Mesa
Branch: main
Commit: 1912503224df2f20cad6b7c125419d4c777ebe9e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1912503224df2f20cad6b7c125419d4c777ebe9e

Author: Timur Kristóf <timur.kristof at gmail.com>
Date:   Fri Jan 21 19:57:42 2022 +0100

radv: Don't disturb dynamic primitive topology with mesh shading.

Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14653>

---

 src/amd/vulkan/radv_cmd_buffer.c |  9 ++++++---
 src/amd/vulkan/radv_pipeline.c   | 16 +++++++---------
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 5476858c7e9..9c4c3e9fd46 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1576,7 +1576,7 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
 {
    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 
-   assert(!cmd_buffer->state.mesh_shading || d->primitive_topology == V_008958_DI_PT_POINTLIST);
+   assert(!cmd_buffer->state.mesh_shading);
 
    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
       radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cmd_buffer->cs,
@@ -5097,8 +5097,11 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
 
       bool mesh_shading = radv_pipeline_has_mesh(pipeline);
       if (mesh_shading != cmd_buffer->state.mesh_shading) {
-         /* Re-emit VRS state because the combiner is different (vertex vs primitive). */
-         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;
+         /* Re-emit VRS state because the combiner is different (vertex vs primitive).
+          * Re-emit primitive topology because the mesh shading pipeline clobbered it.
+          */
+         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE |
+                                    RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY;
       }
 
       cmd_buffer->state.mesh_shading = mesh_shading;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f9973b8ea9f..153e5897b40 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1422,10 +1422,10 @@ radv_pipeline_needed_dynamic_state(const struct radv_pipeline *pipeline,
    /* Disable dynamic states that are useless to mesh shading. */
    if (radv_pipeline_has_mesh(pipeline)) {
       if (has_static_rasterizer_discard)
-         return RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE | RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
+         return RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE;
 
       states &= ~(RADV_DYNAMIC_VERTEX_INPUT | RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE |
-                  RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE);
+                  RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE | RADV_DYNAMIC_PRIMITIVE_TOPOLOGY);
    }
 
    /* If rasterization is disabled we do not care about any of the
@@ -1666,14 +1666,10 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
    }
 
    if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
-      if (radv_pipeline_has_mesh(pipeline)) {
-         dynamic->primitive_topology = V_008958_DI_PT_POINTLIST;
-      } else {
-         dynamic->primitive_topology = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
+      dynamic->primitive_topology = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
 
-         if (extra && extra->use_rectlist) {
-            dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
-         }
+      if (extra && extra->use_rectlist) {
+         dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
       }
    }
 
@@ -5333,6 +5329,8 @@ radv_pipeline_generate_mesh_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_c
 
    radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, ms);
    radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, ms->info.workgroup_size);
+   radeon_set_uconfig_reg_idx(pipeline->device->physical_device, ctx_cs,
+                              R_030908_VGT_PRIMITIVE_TYPE, 1, V_008958_DI_PT_POINTLIST);
 }
 
 static uint32_t