Mesa (staging/21.3): 26 new commits
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Sun Feb 20 20:33:13 UTC 2022
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76ce3eecf41c59f6d33469286ed548056750de8b
Author: Thierry Reding <treding at nvidia.com>
Date: Wed Oct 6 22:47:17 2021 +0200
tegra: Use private reference count for resources
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on resources can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: 7688b8ae9802 ("st/mesa: eliminate all atomic ops when setting vertex buffers")
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Tested-by: Karol Herbst <kherbst at redhat.com>
(cherry picked from commit 108e6eaa83eed3eb356f3cce835c5f5e3a836b8e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16ef6386f14b6a0ddd6d117b3b4cec9318e6b95e
Author: Thierry Reding <treding at nvidia.com>
Date: Wed Oct 6 22:42:36 2021 +0200
tegra: Use private reference count for sampler views
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on sampler views can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: ef5d42741327 ("st/mesa: add a mechanism to bypass atomics when binding sampler views")
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Tested-by: Karol Herbst <kherbst at redhat.com>
(cherry picked from commit e8ce0a335704af54b8269d6e862835703700392b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ae968b433c70cb31f5cc18055d3e6bb9d975bdb
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Sat Feb 12 17:27:41 2022 +0100
radv: Disable IB2 on compute queues.
The "IB2" indirect buffer command is not supported on compute queues
according to PAL, and it indeed causes GPU hangs when task shaders are
used together with vkCmdExecuteCommands.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15006>
(cherry picked from commit da719792ad2b7f50824fd1ba500f8b87e4b3b448)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=206a23b79d0ea6cb70ce8588c51f6a7936a80d56
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Wed Nov 24 17:51:19 2021 +0100
ir3/spill: Fix simplify_phi_nodes with multiple loop nesting
Once we simplified a phi node, we never updated the definition it points
to, which meant that it could become out of date if that definition were
also simplified, and we didn't check that when rewriting sources. That
could happen when there are multiple nested loops with phi nodes at the
header.
Fix it by updating the phi's pointer. Since we always update sources
after visiting the definition it points to, when we go to rewrite a
source, if that source points to a simplified phi, the phi's pointer
can't be pointing to a simplified phi because we already visited the phi
earlier in the pass and updated it, or else it's been simplified in the
meantime and this isn't the last pass. This way we don't need to
keep recursing when rewriting sources.
Fixes: 613eaac7b53 ("ir3: Initial support for spilling non-shared registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15035>
(cherry picked from commit 3ef858a6f6789207e3f24550e9dfb595e3018029)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=896224d9ff8c50cbdcbe3afac5fcfe8bde8c7269
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Feb 15 10:22:15 2022 +0200
mesa/st: always use DXT5 when transcoding ASTC format
This fixes artifacts seen in games when using ASTC transcoding,
we need to use DXT5 for proper alpha channel support.
Number of components is a block specific property, there is no easy
way to see if we will require >1bit alpha support or not, so simply
use DXT5 to have support in place.
Fixes: 91cbe8d855c ("gallium: Add a transcode_astc driconf option")
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15029>
(cherry picked from commit d3b4202b63cb3aca42bc91c5bc416acc1b7f382b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8950adac7683ca5731cb716a603b2d24d6480c54
Author: Yiwei Zhang <zzyiwei at chromium.org>
Date: Tue Feb 15 20:15:57 2022 +0000
venus: properly destroy deferred ahb image before real image creation
Fixes: 19b7b09885c ("venus: prepare image creation helpers for AHB")
Signed-off-by: Yiwei Zhang <zzyiwei at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15037>
(cherry picked from commit 9dd15295e30b3dd5a75440dab05a1eb4019ef1a8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbbb0e1ccf1a0f213a6f971d819e08143898cba0
Author: Emma Anholt <emma at anholt.net>
Date: Sat Feb 5 20:11:25 2022 -0800
i915g: Initialize the rest of the "from_nir" temporary VS struct.
draw looked at the uninitialized XFB state, which should just be zeroed
out since i915 doesn't have XFB.
Fixes: 2b3fc26da8be ("i915g: Switch to using nir-to-tgsi.")
Reviewed-by: Zoltán Böszörményi <zboszor at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14896>
(cherry picked from commit 780949c62bc2cd1805f99911a76fde016e430b6b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e40263d9cf4499fac28d8a0a74aeceb0e1a94459
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Feb 14 07:40:51 2022 +0200
iris: fix a leak on surface states
Cc: mesa-stable
Closes:https://gitlab.freedesktop.org/mesa/mesa/-/issues/6013
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15010>
(cherry picked from commit ecc00410302cae4e22ad7718a531f03658190389)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d0c2111eb302bbea79774f3824d432557808642
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sat Jan 15 14:43:15 2022 +0100
radv: Fix preamble argument order.
Used the wrong cmdbuffer in the wrong situation. Oops.
Fixes: 915e9178faf ("radv: Split out commandbuffer submission.")
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14574>
(cherry picked from commit 79131b6ee6c98a8b662aeb32bb623a8974f8bef5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3259733da851909b22c9ff4a3c876f11e0abd1a
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Feb 11 11:17:49 2022 +0100
radv/winsys: fix initializing debug/perftest options if multiple instances
Since the winsys uses refcount, options like RADV_DEBUG_ZERO_VRAM might
have not been initialized if the first instance wasn't created with
application info.
This fixes missing zerovram for vkd3d-proton.
Cc: 21.3 22.0 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14978>
(cherry picked from commit aa3405e8123324b3d8173c709e6573d86570d99a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d9a4fd95e01b7aec7d47989e1f34aac42f4d451
Author: Eric Engestrom <eric at engestrom.ch>
Date: Sun Feb 20 16:28:09 2022 +0000
.pick_status.json: Mark b07372312d7053f2ef5c858ceb1fbf9ade5e7c52 as denominated
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a01a01e6e1a43f696fd5bfda94de11e6c9f4003
Author: Jason Ekstrand <jason.ekstrand at collabora.com>
Date: Tue Feb 8 16:04:34 2022 -0600
anv: Call vk_command_buffer_finish if create fails
This wasn't much of a problem before because vk_command_buffer_finish()
doesn't do much on an empty command buffer. However, it's about to be
responsible for managing the pool's list of command buffers so it will
be critical to get this right.
Fixes: c9189f481353 ("anv: Use a common vk_command_buffer structure")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14917>
(cherry picked from commit 7b0e30685446d30aaea1c2c7c1fd04a658c74d94)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae51b486038d338a9e245c38dda80602dc99aefa
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 10:50:55 2021 -0700
nir: Produce correct results for atan with NaN
Properly handling NaN adversely affects several hundred shaders in
shader-db (lots of Skia and a few others from various synthetic
benchmarks) and fossil-db (mostly Talos and some Doom 2016). Only apply
the NaN handling work-around when the shader demands it.
v2: Add comment explaining the 1.0*y_over_x. Suggested by Caio.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 2098ae16c8b ("nir/builder: Move nir_atan and nir_atan2 from SPIR-V translator")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 1cb3d1a6ae027b5045e47ccf7e551bd81fc3cab2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=be964326971ff575d56895095f2d7ec0e64159d8
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 28 17:34:56 2021 -0700
nir: Properly handle various exceptional values in frexp
frexp_sig of ±0, ±Inf, or NaN should just return the input unmodified.
frexp_exp of ±Inf or NaN is undefined, and frexp_exp of ±0 should return
the input unmodified. This seems to already work.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 23d30f4099f ("spirv,nir: lower frexp_exp/frexp_sig inside a new NIR pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 7d0d9b9fbc231c2bd66778e0b0a62d5c514c5495)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a073ed564f3839d0857cd03388ffd4f70b88dff5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 10:51:25 2021 -0700
spirv: Produce correct result for GLSLstd450Tanh with NaN
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 9f9432d56c0 ("Revert "spirv: Use a simpler and more correct implementaiton of tanh()"")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 93ed87af28e7f5b7db7bae095e5a37b63b7bd2c7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba195357f76a6c8e97b75013617cf558d2cf7a77
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 08:15:18 2021 -0700
spirv: Produce correct result for GLSLstd450Modf with Inf
GLSLstd450ModfStruct too.
No shader-db or fossil-db changes on any Intel platform.
v2: Fix handling 16-bit (and presumably 64-bit) values.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: f92a35d831c ("vtn: Fix Modf.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit e442b9d79296ad9322af61fdadbc81d680466f57)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cb72c4697582df7bad141f9da545e7734c69df4
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 28 17:33:02 2021 -0700
spriv: Produce correct result for GLSLstd450Step with NaN
NOTE: This commit needs "nir: All set-on-comparison opcodes can take all
float types" or regressions will occur in other Vulkan SPIR-V tests.
No shader-db changes on any Intel platform.
NOTE: This commit depends on "nir: All set-on-comparison opcodes can
take all float types".
v2: Fix handling 16-bit (and presumably 64-bit) values.
About 280 shaders in Talos are hurt by a few instructions, and a couple
shaders in Doom 2016 are hurt by a few instructions.
Tiger Lake
Instructions in all programs: 159893290 -> 159895026 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019260087 -> 7019254134 (-0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)
Ice Lake
Instructions in all programs: 143624235 -> 143625691 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440083238 -> 8440090702 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)
Skylake
Instructions in all programs: 134185495 -> 134186618 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366923 -> 8222365826 (-0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 1feeee9cf47 ("nir/spirv: Add initial support for GLSL 4.50 builtins")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 75ef5991f5af06997551dabc053300261e32ca40)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9806ecf10098c3b0f8b9b9af7056405bc0d04f9
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 14:16:44 2021 -0700
intel/fs: Don't optimize out 1.0*x and -1.0*x
This (sort of) matches the behavior of nir_opt_algebraic. This ensures
that subnormal values are properly flushed to zero.
With the aid of "nir/search: Float sources of texture instructions are
float users" and "nir/search: Transitively apply is_only_used_as_float",
there would have been no shader-db regressions on Intel platforms.
However, those caused a significant increase in compile time. Since the
instruction regressions were so small, I just dropped those commits
rather than improve them.
All Haswell and newer platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20125042 -> 20125094 (<.01%)
instructions in affected programs: 7184 -> 7236 (0.72%)
helped: 0
HURT: 32
HURT stats (abs) min: 1 max: 4 x̄: 1.62 x̃: 2
HURT stats (rel) min: 0.11% max: 1.49% x̄: 0.85% x̃: 0.78%
95% mean confidence interval for instructions value: 1.39 1.86
95% mean confidence interval for instructions %-change: 0.74% 0.96%
Instructions are HURT.
total cycles in shared programs: 862745586 -> 862746551 (<.01%)
cycles in affected programs: 109872 -> 110837 (0.88%)
helped: 12
HURT: 23
helped stats (abs) min: 2 max: 774 x̄: 90.83 x̃: 19
helped stats (rel) min: 0.07% max: 25.23% x̄: 3.06% x̃: 0.40%
HURT stats (abs) min: 2 max: 1106 x̄: 89.35 x̃: 12
HURT stats (rel) min: 0.08% max: 45.40% x̄: 3.01% x̃: 0.47%
95% mean confidence interval for cycles value: -60.09 115.23
95% mean confidence interval for cycles %-change: -2.21% 4.07%
Inconclusive result (value mean confidence interval includes 0).
All of the shaders hurt are in either UE4 shooter-game or shooter_demo.
Tiger Lake
Instructions in all programs: 159893213 -> 159893290 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019259514 -> 7019260087 (+0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)
Ice Lake
Instructions in all programs: 143624164 -> 143624235 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440082767 -> 8440083238 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)
Skylake
Instructions in all programs: 134185424 -> 134185495 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366529 -> 8222366923 (+0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: f5dd6dfe012 ("anv: enable VK_KHR_shader_float_controls and SPV_KHR_float_controls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 38a94c82e6ac3ae3e76e01ff4994ae4c46c487ec)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9883f7fb0ec56f2f73f085ad7311919054f01e6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 30 09:45:49 2021 -0800
nir: All set-on-comparison opcodes can take all float types
Extend 4195a9450bde so that the next poor fool doesn't come along and
say, "sge does the right thing for 16-bit sources, but slt gives a NIR
validation failure. What the deuce?"
NOTE: This commit is necessary to prevent regressions in GLSLstd450Step
tests of 16-bit sources at "spriv: Produce correct result for
GLSLstd450Step with NaN".
Fixes: 4195a9450bd ("nir: sge operation is defined for floating-point types")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 38800b385c6b4752ec1a91db5b8a7de149d03d0c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e3e06a424d578aecef30d6521951f2e1b68c3ab
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Dec 27 10:15:19 2021 -0500
iris: Don't fast clear with the view format
Fast clear with the resource format instead. This is safe to do because
can_fast_clear_color ensures that the clear color generates the same
pixel with either the view format or the resource format.
On SKL, this prevents us from using an invalid surface state. This platform
doesn't support CCS_E with sRGB formats, but prior to this patch we allowed
fast-clearing with this combination. Piglit's fcc-write-after-clear test
can trigger this.
Fixes: 230952c2101 ("iris: Don't support sRGB + Y_TILED_CCS on gen9")
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>
(cherry picked from commit 6778b3a379d010d9b4d82e7324bff19d73cd3d1a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5914b0157efa561c3bb9c062e1d80ca16330a524
Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date: Wed Feb 9 09:07:41 2022 -0500
aux/draw: fix llvm tcs lane vec generation
the idx param for LLVMBuildInsertElement is zero-indexed based on the
value of 'vector_length' (always 4), and the vector length is (obviously)
sized to 'vector_length', so this should be the member of the vec that is being
inserted, not the invocation index
cc: mesa-stable
fixes (zink, but only on my one machine):
KHR-GL46.tessellation_shader.single.max_patch_vertices
KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
dEQP-GLES31.functional.tessellation.shader_input_output.barrier
dEQP-GLES31.functional.tessellation.shader_input_output.patch_vertices_5_in_10_out
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_point_mode_geometry_output_triangles
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_point_mode_geometry_output_lines
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_point_mode_geometry_output_lines
Reviewed-by: Dave Airlie <airlied at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14949>
(cherry picked from commit 68c1b50e48e32ec8ff4815666b7124d4cb4171ab)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c076b3cedc483ff991b18451f4b71d3db41b19d6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 8 17:53:02 2022 -0800
gallivm/nir: Call nir_lower_bool_to_int32 after nir_opt_algebraic_late
All of the opcodes in nir_opt_algebraic_late are the unsized (1-bit)
versions. If the lowering to int32 happens first, many of the
optimizations and lowerings won't happen.
Of particular importance is the lowering of fisfinite. If a shader
happens to contain fisfinite of an fp16 value, it will assert later
during compliation.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Fixes: 78b4e417d44 ("gallivm: handle fisfinite/fisnormal")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14942>
(cherry picked from commit e3cbc328e0dbb5865cc036ecbf977127850b4670)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb2f42ee01cd5393eb0f5bc29dd97531089e9938
Author: Qiang Yu <yuq825 at gmail.com>
Date: Wed Feb 9 09:40:22 2022 +0800
radeonsi: workaround Specviewperf13 Catia hang on GFX9
The root cause is unknown but PAL always update IA_MULTI_VGT_PARAM
whenever primitive type change.
cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Singed-off-by: Qiang Yu <yuq825 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14944>
(cherry picked from commit fe560aeb12516e766335d416ba749b7572637274)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=71fa224c1bca5a6345409d7be832b1a7d2b2d418
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jan 31 11:52:21 2022 +0200
iris: invalidate L3 read only cache when VF cache is invalidated
When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.
Ref: bspec 46314
Fixes: ed8f2c4cbee ("iris: Cache VB/IB in L3$ for Gen12")
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 562f7eef5b4f5a4d4fb4d93418e6373e853550fa)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1921d19058d83a6f0fdd253c8f9850bd8a52ca53
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jan 31 11:49:53 2022 +0200
anv: invalidate L3 read only cache when VF cache is invalidated
When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.
Ref: bspec 46314
Fixes: 6c345ddbe40 ("anv: Cache VB/IB in L3$ for Gfx12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5941
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 7a6ea047954461d8f61878494265ba4bb84b50fe)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a49692f763f4c146b7a5573aedf3edf5e60e6361
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jan 31 11:48:49 2022 +0200
intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 442628b70244f2c9fd0ed79e0656e999ee6fffca)
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