Mesa (main): radv/winsys: add support for new CTX OP to set/get stable pstates

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 5cf4f0cc9197c2baed4395c12f6e9dc81ee9eae4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cf4f0cc9197c2baed4395c12f6e9dc81ee9eae4

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Dec  3 09:03:31 2021 +0100

radv/winsys: add support for new CTX OP to set/get stable pstates

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14038>

---

 src/amd/vulkan/radv_radeon_winsys.h           | 10 ++++++++++
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 28 +++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index 047e07afa22..d72b4d670d8 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -77,6 +77,14 @@ enum radeon_ctx_priority {
    RADEON_CTX_PRIORITY_REALTIME,
 };
 
+enum radeon_ctx_pstate {
+   RADEON_CTX_PSTATE_NONE = 0,
+   RADEON_CTX_PSTATE_STANDARD,
+   RADEON_CTX_PSTATE_MIN_SCLK,
+   RADEON_CTX_PSTATE_MIN_MCLK,
+   RADEON_CTX_PSTATE_PEAK,
+};
+
 enum radeon_value_id {
    RADEON_ALLOCATED_VRAM,
    RADEON_ALLOCATED_VRAM_VIS,
@@ -250,6 +258,8 @@ struct radeon_winsys {
 
    bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type, int ring_index);
 
+   int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate);
+
    enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
 
    struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum ring_type ring_type);
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 9b4f34df7bd..907588c25d6 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -1576,6 +1576,33 @@ radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx, enum ring_type ring_t
    return true;
 }
 
+static uint32_t
+radv_to_amdgpu_pstate(enum radeon_ctx_pstate radv_pstate)
+{
+   switch (radv_pstate) {
+   case RADEON_CTX_PSTATE_NONE:
+      return AMDGPU_CTX_STABLE_PSTATE_NONE;
+   case RADEON_CTX_PSTATE_STANDARD:
+      return AMDGPU_CTX_STABLE_PSTATE_STANDARD;
+   case RADEON_CTX_PSTATE_MIN_SCLK:
+      return AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK;
+   case RADEON_CTX_PSTATE_MIN_MCLK:
+      return AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK;
+   case RADEON_CTX_PSTATE_PEAK:
+      return AMDGPU_CTX_STABLE_PSTATE_PEAK;
+   default:
+      unreachable("Invalid pstate");
+   }
+}
+
+static int
+radv_amdgpu_ctx_set_pstate(struct radeon_winsys_ctx *rwctx, enum radeon_ctx_pstate pstate)
+{
+   struct radv_amdgpu_ctx *ctx = (struct radv_amdgpu_ctx *)rwctx;
+   uint32_t amdgpu_pstate = radv_to_amdgpu_pstate(pstate);
+   return amdgpu_cs_ctx_stable_pstate(ctx->ctx, AMDGPU_CTX_OP_SET_STABLE_PSTATE, amdgpu_pstate, NULL);
+}
+
 static void *
 radv_amdgpu_cs_alloc_syncobj_chunk(struct radv_winsys_sem_counts *counts, uint32_t queue_syncobj,
                                    struct drm_amdgpu_cs_chunk *chunk, int chunk_id)
@@ -1803,6 +1830,7 @@ radv_amdgpu_cs_init_functions(struct radv_amdgpu_winsys *ws)
    ws->base.ctx_create = radv_amdgpu_ctx_create;
    ws->base.ctx_destroy = radv_amdgpu_ctx_destroy;
    ws->base.ctx_wait_idle = radv_amdgpu_ctx_wait_idle;
+   ws->base.ctx_set_pstate = radv_amdgpu_ctx_set_pstate;
    ws->base.cs_domain = radv_amdgpu_cs_domain;
    ws->base.cs_create = radv_amdgpu_cs_create;
    ws->base.cs_destroy = radv_amdgpu_cs_destroy;