Mesa (main): broadcom/compiler: fix register class patching for postponed spills

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Module: Mesa
Branch: main
Commit: c4a78a2d2a0b78a42cabd4e75f081d08f4f22e9c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4a78a2d2a0b78a42cabd4e75f081d08f4f22e9c

Author: Iago Toral Quiroga <itoral at igalia.com>
Date:   Tue Feb 22 10:27:00 2022 +0100

broadcom/compiler: fix register class patching for postponed spills

If we have a postponed spill, the temp we create at ip is no longer
the spilled temp and therefore is affected by the thrsw injection.

Fixes corruption in the additive blending animation demo from
Three.js.

Fixes: f3c3228522 ('broadcom/compiler: do not rebuild the interference graph after each spill')
Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15112>

---

 src/broadcom/compiler/vir_register_allocate.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/broadcom/compiler/vir_register_allocate.c b/src/broadcom/compiler/vir_register_allocate.c
index 6336d19686e..23212df139f 100644
--- a/src/broadcom/compiler/vir_register_allocate.c
+++ b/src/broadcom/compiler/vir_register_allocate.c
@@ -352,14 +352,15 @@ v3d_emit_spill_tmua(struct v3d_compile *c,
          * is not affected by the thrsw. Something that ends at ip will be
          * affected though.
          *
-         * Spills inject code after ip, so anything that starts later than ip
-         * is not affected (and only the spilled temp starts at ip). Something
-         * that ends at ip won't be affected either.
+         * Spills inject code after ip, so anything that starts strictly later
+         * than ip is not affected (the temp starting at ip is usually the
+         * spilled temp except for postponed spills). Something that ends at ip
+         * won't be affected either.
          */
         for (int i = 0; i < c->spill_start_num_temps; i++) {
                 bool thrsw_cross = fill_dst ?
                         c->temp_start[i] < ip && c->temp_end[i] >= ip :
-                        c->temp_start[i] < ip && c->temp_end[i] > ip;
+                        c->temp_start[i] <= ip && c->temp_end[i] > ip;
                 if (thrsw_cross) {
                         ra_set_node_class(c->g, c->ra_map.temp[i].node,
                                           choose_reg_class(c, CLASS_BITS_PHYS));