Mesa (staging/22.0): 61 new commits
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Thu Feb 24 22:57:09 UTC 2022
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0669175798b0c7199dd23cb96c52d68a64ede76
Author: Dylan Baker <dylan.c.baker at intel.com>
Date: Wed Feb 23 10:32:14 2022 -0800
version: bump for 22.0.0-rc3 release
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c94e7e7247213c52e0689c48057e03625d23007
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 16 14:02:16 2022 -0800
nir: Add missing dependency on nir_opcodes.py
Commit 38800b38 changed nir_opcodes.py, but that doesn't seem to have
triggered nir_opt_algebraic.py. The change in 75ef5991 depends on
opt_algebraic lowering 16-bit versions of slt, but if opt_algebraic is
not rebuilt, this may not happen. This resulted in some people seeing
assertion failures in, for example,
dEQP-VK.spirv_assembly.instruction.compute.float16.arithmetic_3.step,
due to the backend seeing nir_op_slt that it didn't know how to handle.
v2: Add nir_opcodes.py to nir_algebraic_py so that all the per-driver
algebraic passes pick up the dependency too. Rename it to
nir_algebraic_depends. Suggested by Emma.
Closes: #6047
Fixes: d1992255bb2 ("meson: Add build Intel "anv" vulkan driver")
Reviewed-by: Emma Anholt <emma at anholt.net>
Acked-by: Dave Airlie <airlied at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15050>
(cherry picked from commit a01b26299039496ca7ed04878cbb64a18af3037c)
Conflicts:
src/gallium/drivers/r300/meson.build
- Delete code from r300, which doesn't exist in the 22.0 branch
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=60ad4707d4834e4c76e62a0934568dab3e7d6409
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Fri Feb 18 19:20:27 2022 -0500
pan/bi: Specialize IDVS in NIR
It's a bit more code, but it's needed to chew through control flow since we
don't have a backend version of dead_cf. Results are really good, meaning I
really screwed this up the first time around (hence the cc mesa-stable).
total instructions in shared programs: 1963576 -> 1939513 (-1.23%)
instructions in affected programs: 671053 -> 646990 (-3.59%)
helped: 4436
HURT: 729
helped stats (abs) min: 1.0 max: 43.0 x̄: 5.75 x̃: 6
helped stats (rel) min: 0.21% max: 100.00% x̄: 6.47% x̃: 5.17%
HURT stats (abs) min: 1.0 max: 22.0 x̄: 2.01 x̃: 1
HURT stats (rel) min: 0.50% max: 50.00% x̄: 10.45% x̃: 9.09%
95% mean confidence interval for instructions value: -4.77 -4.55
95% mean confidence interval for instructions %-change: -4.36% -3.80%
Instructions are helped.
total tuples in shared programs: 1533335 -> 1523194 (-0.66%)
tuples in affected programs: 483167 -> 473026 (-2.10%)
helped: 3414
HURT: 1288
helped stats (abs) min: 1.0 max: 20.0 x̄: 3.73 x̃: 2
helped stats (rel) min: 0.27% max: 100.00% x̄: 4.87% x̃: 3.03%
HURT stats (abs) min: 1.0 max: 19.0 x̄: 2.02 x̃: 1
HURT stats (rel) min: 0.24% max: 38.10% x̄: 8.10% x̃: 5.88%
95% mean confidence interval for tuples value: -2.28 -2.03
95% mean confidence interval for tuples %-change: -1.62% -1.02%
Tuples are helped.
total clauses in shared programs: 351432 -> 329158 (-6.34%)
clauses in affected programs: 142237 -> 119963 (-15.66%)
helped: 5328
HURT: 3
helped stats (abs) min: 1.0 max: 43.0 x̄: 4.18 x̃: 4
helped stats (rel) min: 0.74% max: 100.00% x̄: 19.44% x̃: 17.24%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 9.09% max: 12.50% x̄: 10.90% x̃: 11.11%
95% mean confidence interval for clauses value: -4.25 -4.11
95% mean confidence interval for clauses %-change: -19.72% -19.12%
Clauses are helped.
total cycles in shared programs: 202830.92 -> 172084.50 (-15.16%)
cycles in affected programs: 117078.42 -> 86332 (-26.26%)
helped: 5450
HURT: 1
helped stats (abs) min: 0.083333 max: 49.0 x̄: 5.64 x̃: 5
helped stats (rel) min: 1.42% max: 100.00% x̄: 27.94% x̃: 25.64%
HURT stats (abs) min: 0.25 max: 0.25 x̄: 0.25 x̃: 0
HURT stats (rel) min: 2.46% max: 2.46% x̄: 2.46% x̃: 2.46%
95% mean confidence interval for cycles value: -5.74 -5.54
95% mean confidence interval for cycles %-change: -28.30% -27.58%
Cycles are helped.
total arith in shared programs: 57274.29 -> 57145.04 (-0.23%)
arith in affected programs: 16418.33 -> 16289.08 (-0.79%)
helped: 2442
HURT: 1784
helped stats (abs) min: 0.041665999999999315 max: 0.75 x̄: 0.14 x̃: 0
helped stats (rel) min: 0.23% max: 100.00% x̄: 5.51% x̃: 2.87%
HURT stats (abs) min: 0.041665999999999315 max: 0.9166670000000003 x̄: 0.12 x̃: 0
HURT stats (rel) min: 0.00% max: 100.00% x̄: 25.13% x̃: 9.09%
95% mean confidence interval for arith value: -0.04 -0.03
95% mean confidence interval for arith %-change: 6.61% 8.24%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total texture in shared programs: 12857 -> 12857 (0.00%)
texture in affected programs: 0 -> 0
helped: 0
HURT: 0
total vary in shared programs: 11157.75 -> 11157.75 (0.00%)
vary in affected programs: 0 -> 0
helped: 0
HURT: 0
total ldst in shared programs: 177208 -> 146420 (-17.37%)
ldst in affected programs: 117098 -> 86310 (-26.29%)
helped: 5447
HURT: 0
helped stats (abs) min: 1.0 max: 49.0 x̄: 5.65 x̃: 5
helped stats (rel) min: 1.92% max: 100.00% x̄: 27.91% x̃: 25.64%
95% mean confidence interval for ldst value: -5.75 -5.55
95% mean confidence interval for ldst %-change: -28.27% -27.56%
Ldst are helped.
total quadwords in shared programs: 1436507 -> 1398329 (-2.66%)
quadwords in affected programs: 515101 -> 476923 (-7.41%)
helped: 5150
HURT: 111
helped stats (abs) min: 1.0 max: 39.0 x̄: 7.46 x̃: 6
helped stats (rel) min: 0.17% max: 100.00% x̄: 10.02% x̃: 8.24%
HURT stats (abs) min: 1.0 max: 9.0 x̄: 2.01 x̃: 1
HURT stats (rel) min: 0.43% max: 21.62% x̄: 3.57% x̃: 1.94%
95% mean confidence interval for quadwords value: -7.41 -7.11
95% mean confidence interval for quadwords %-change: -9.98% -9.49%
Quadwords are helped.
total threads in shared programs: 35025 -> 35228 (0.58%)
threads in affected programs: 218 -> 421 (93.12%)
helped: 208
HURT: 5
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel) min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.91 0.99
95% mean confidence interval for threads %-change: 93.40% 99.55%
Threads are helped.
total loops in shared programs: 128 -> 125 (-2.34%)
loops in affected programs: 3 -> 0
helped: 3
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
total spills in shared programs: 158 -> 149 (-5.70%)
spills in affected programs: 15 -> 6 (-60.00%)
helped: 9
HURT: 0
total fills in shared programs: 1133 -> 966 (-14.74%)
fills in affected programs: 197 -> 30 (-84.77%)
helped: 9
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
(cherry picked from commit e0e63c2a8e6dba9d5806aebe355f16a0431fe64b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7364245060c5410a8f3e814550bf3a2528437b6
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Sun Feb 20 21:29:50 2022 -0500
panvk: Use more reliable assert for UBO pushing
The important thing isn't the number of words pushed, it's that there are no
UBOs required for us to upload. Check that instead.
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15090>
(cherry picked from commit 3c1021cd1ed0f60d474a6c3a6aafb0746f1da02b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07a9bc76d3ce0b63132132542f3b8d4e10583d2b
Author: Dylan Baker <dylan.c.baker at intel.com>
Date: Tue Feb 22 12:09:06 2022 -0800
.pick_status.json: Mark a8418abd748e8e761dda9c3594e29e560833d9ff as denominated
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8d25b50c96e2a706092c26933dd02d5005ea4d9
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Fri Jul 23 16:49:02 2021 -0400
pan/bi: Lower swizzles on CSEL.i32/MUX.i32
This is counter-intuitive, but required for correct operation when
CSEL.i32 takes a 1-bit (stored 16-bit) boolean argument. The impedance
mismatch ultimately is between CSEL.b32 (nir's bcsel, nonexistant in the
hardware) and the lowering CSEL.i32. However, a similar problem exists
even with MUX.i32 which lacks a good way of zero/sign-extending
booleans.
Cherry-picked from my Valhall branch though the issue also affects
Bifrost. Fixes piglit shaders at glsl-vs-if-bool on Bifrost.
Unfortunately, shader-db is quite unhappy :-(
The proper fix is to use lower_bool_to_bitsize, but that can't be
backported to mesa-stable.
total instructions in shared programs: 157539 -> 158953 (0.90%)
instructions in affected programs: 55621 -> 57035 (2.54%)
helped: 2
HURT: 259
helped stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
helped stats (rel) min: 2.11% max: 2.67% x̄: 2.39% x̃: 2.39%
HURT stats (abs) min: 1.0 max: 40.0 x̄: 5.47 x̃: 2
HURT stats (rel) min: 0.36% max: 16.13% x̄: 2.55% x̃: 1.59%
95% mean confidence interval for instructions value: 4.44 6.40
95% mean confidence interval for instructions %-change: 2.21% 2.82%
Instructions are HURT.
total tuples in shared programs: 132322 -> 132907 (0.44%)
tuples in affected programs: 31806 -> 32391 (1.84%)
helped: 5
HURT: 152
helped stats (abs) min: 1.0 max: 2.0 x̄: 1.40 x̃: 1
helped stats (rel) min: 0.39% max: 3.03% x̄: 1.70% x̃: 1.61%
HURT stats (abs) min: 1.0 max: 42.0 x̄: 3.89 x̃: 2
HURT stats (rel) min: 0.29% max: 18.18% x̄: 2.50% x̃: 1.79%
95% mean confidence interval for tuples value: 2.88 4.58
95% mean confidence interval for tuples %-change: 1.87% 2.85%
Tuples are HURT.
total clauses in shared programs: 28672 -> 28698 (0.09%)
clauses in affected programs: 869 -> 895 (2.99%)
helped: 1
HURT: 24
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 5.88% max: 5.88% x̄: 5.88% x̃: 5.88%
HURT stats (abs) min: 1.0 max: 2.0 x̄: 1.12 x̃: 1
HURT stats (rel) min: 0.49% max: 33.33% x̄: 8.46% x̃: 3.59%
95% mean confidence interval for clauses value: 0.82 1.26
95% mean confidence interval for clauses %-change: 3.84% 11.93%
Clauses are HURT.
total cycles in shared programs: 15119.04 -> 15137.88 (0.12%)
cycles in affected programs: 922.87 -> 941.71 (2.04%)
helped: 4
HURT: 79
helped stats (abs) min: 0.0416669999999999 max: 0.0833330000000001 x̄: 0.05 x̃: 0
helped stats (rel) min: 0.40% max: 3.17% x̄: 1.57% x̃: 1.35%
HURT stats (abs) min: 0.041665999999999315 max: 1.75 x̄: 0.24 x̃: 0
HURT stats (rel) min: 0.30% max: 20.00% x̄: 2.83% x̃: 2.12%
95% mean confidence interval for cycles value: 0.17 0.29
95% mean confidence interval for cycles %-change: 1.86% 3.37%
Cycles are HURT.
total arith in shared programs: 4922.71 -> 4947.71 (0.51%)
arith in affected programs: 1423.79 -> 1448.79 (1.76%)
helped: 5
HURT: 177
helped stats (abs) min: 0.0416669999999999 max: 0.0833330000000001 x̄: 0.06 x̃: 0
helped stats (rel) min: 0.40% max: 3.17% x̄: 1.82% x̃: 1.67%
HURT stats (abs) min: 0.041665999999999315 max: 1.75 x̄: 0.14 x̃: 0
HURT stats (rel) min: 0.30% max: 22.22% x̄: 2.50% x̃: 1.52%
95% mean confidence interval for arith value: 0.11 0.17
95% mean confidence interval for arith %-change: 1.86% 2.90%
Arith are HURT.
total quadwords in shared programs: 120605 -> 120956 (0.29%)
quadwords in affected programs: 26535 -> 26886 (1.32%)
helped: 6
HURT: 143
helped stats (abs) min: 1.0 max: 7.0 x̄: 2.83 x̃: 1
helped stats (rel) min: 0.93% max: 6.33% x̄: 2.29% x̃: 1.71%
HURT stats (abs) min: 1.0 max: 21.0 x̄: 2.57 x̃: 2
HURT stats (rel) min: 0.34% max: 13.79% x̄: 2.02% x̃: 1.22%
95% mean confidence interval for quadwords value: 1.86 2.86
95% mean confidence interval for quadwords %-change: 1.45% 2.24%
Quadwords are HURT.
total threads in shared programs: 4670 -> 4669 (-0.02%)
threads in affected programs: 2 -> 1 (-50.00%)
helped: 0
HURT: 1
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14576>
(cherry picked from commit 8bd4976d981a9a98ce7e419b25c05d38ccac027b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd29a0689bcaa3d4f0264500e6b9072b11c7eb58
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Thu Feb 17 19:34:04 2022 -0500
pan/bi: Avoid *FADD.v2f16 hazard in scheduler
Obscure encoding restriction. Fixes crash (assertion fail when instruction
packing) in asphalt9/2659.shader_test on Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072>
(cherry picked from commit 24d2bdb1e050134a25924487792ee0018f8478ae)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=183e19f23adb9e1d4ff40ead1cd088998e65445a
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Thu Feb 17 19:33:29 2022 -0500
pan/bi: Avoid *FADD.v2f16 hazard in optimizer
This is a very obscure encoding restriction in the Bifrost ISA. Unknown if any
real apps or tests hit this, but we still need to get it right sadly.
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15072>
(cherry picked from commit 8e0eb592d5bbcf00f8bed55cc95013abf77fad12)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b9bc8ad642da3c4fbb1954bc27241a509698fb1
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Thu Feb 17 10:57:47 2022 +0100
ac/nir/ngg: Fix mixed up primitive ID after culling.
When NGG culling is enabled, make sure that the correct
primitive ID is exported by each lane.
Fixes: e97f0463a8f55d5d407178f74b0cdb916a42aef8 "ac/nir: Implement NGG deferred attribute culling in NIR."
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6050
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15055>
(cherry picked from commit 3759a16d8a883355effa435f46867951ce712dbe)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea23bb04f4a376d68f341dbdcc566a17c0cd2458
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Feb 21 23:25:06 2022 -0500
ac/surface: add more elements to meta equations because HTILE can use them
according to gfx10SwizzlePattern.h
Fixes: 9fabbf2150253d06d - ac/surface: copy the HTILE equations to the surface
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
(cherry picked from commit 79a7ab642ac1e103c9b00e197105eb3f10c6c523)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e28013062671062d6cb43e6fd479138935bce807
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 1 11:34:13 2022 -0500
amd: add a workaround for an SQ perf counter bug
Cc: mesa-stable at lists.freedesktop.org
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
(cherry picked from commit 197467c23847793950c9b6e482a0b7f45478da88)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1e61f595d461302a92c598cbedef767375f8d28
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 18 22:23:55 2022 -0500
winsys/radeon: fix a hang due to introducing spi_cu_en
Fixes: 5406ad93 "radeonsi: set COMPUTE_DESTINATION_EN_SEn to spi_cu_en"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5989
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15098>
(cherry picked from commit 707a94f3c5d25601972dcf7c3f569acf8145324f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f56bad4dd4ff25e78e5404de50518fd0817f1e5
Author: Qiang Yu <yuq825 at gmail.com>
Date: Wed Feb 9 16:00:30 2022 +0800
glx: fix pbuffer refcount init
glXMakeCurrent* may miss release pbuffer if pbuffer is created
with refcount=0. This won't happen when pbuffer had different
GLX id and X pixmap id.
cc: mesa-stable
Fixes: bc8a51a79a5 ("glx: no need to create extra pixmap for pbuffer")
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Signed-off-by: Qiang Yu <yuq825 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14926>
(cherry picked from commit bf09c08e315280da340690aa5bdf9ea1ff738108)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c454ff42f07898f4a32d484940795dfa01a28cdf
Author: Marcin Ślusarz <marcin.slusarz at intel.com>
Date: Tue Feb 1 14:39:39 2022 +0100
anv: don't set color state when input state was requested
Fixes: 814dc669359 ("anv: Allocate surface states per-subpass")
Reviewed-by: Jason Ekstrand <jason.ekstrand at collabora.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15081>
(cherry picked from commit 037e98a10c4a4e719fe243f9a39074d3f77c00d7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0906f9f7d297a787587d281e92aa9f591541d5ad
Author: Qiang Yu <yuq825 at gmail.com>
Date: Fri Feb 11 15:01:25 2022 +0800
radeonsi: fix depth stencil multi sample texture blit
This causes the flushed_depth_texture is allocated without
multi sample. So the blit will cause VM fault.
cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Qiang Yu <yuq825 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14990>
(cherry picked from commit 80974a5f1e4095b7ae9b4e705da5b33f283e35c2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6353a869ca65d8d3c46f0a82c848fa7d409a87b9
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Feb 21 09:35:00 2022 +1000
crocus: fix leak on gen4/5 stencil fallback blit path.
Noticed by Ilia.
Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15100>
(cherry picked from commit 0f989a840efda4aedee2dbf009c400c428be01d7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fdd351cc8108db7d6922b344f36fbab14a69bbf1
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Mon Jan 31 12:43:04 2022 +0000
anv/genxml/intel/fs: fix binding shader record entry
Bit is flipped compared to all the other packets.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: 705395344d25 ("intel/fs: Add support for compiling bindless shaders with resume shaders")
Fixes: c3ac9afca389 ("anv: Create and return ray-tracing pipeline SBT handles")
Acked-by: Jason Ekstrand <jason.ekstrand at collabora.com>
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15078>
(cherry picked from commit 2763a8af5ac3739c677ed7de7bd2a7e60a35f822)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5998d19a9605f50f22a498eab1e1c4895c433dcc
Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date: Wed Feb 16 23:14:15 2022 +0200
nir: fix lower_memcpy
memcpy is divided into chunks that are vec4 sized max. The problem
here happens with a structure of 24 bytes :
struct {
float3 a;
float3 b;
}
If you memcpy that struct, the lowering will emit 2 load/store, one of
sized 8, next one sized 16. But both end up located at offset 0, so we
effectively drop 2 floats.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Fixes: a3177cca996145 ("nir: Add a lowering pass to lower memcpy")
Reviewed-by: Jason Ekstrand <jason.ekstrand at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15049>
(cherry picked from commit 768930a73a43e48172df00b6c934de582bd9422b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4aa73d53108d1c2ce4e993cd515c461def2270c5
Author: Jason Ekstrand <jason.ekstrand at collabora.com>
Date: Wed Feb 16 14:51:21 2022 -0600
anv: Don't assume depth/stencil attachments have depth
If a secondary command buffer is used and the client provides a
framebuffer and that framebuffer has a stencil-only attchment, we would
try to get the aux usage for the depth component of that attachment and
crash. Check the aspects of the image before looking at aux usage.
This fixes at least the following SkQP tests on my Tigerlake:
- vk_circular-clips
- vk_filterfastbounds
- vk_innershapes_bw
- vk_lineclosepath
- vk_multipicturedraw_rrectclip_simple
- vk_pathinvfill
- vk_quadclosepath
- vk_rrect_clip_bw
- vk_windowrectangles
Fixes: 0d8b9c529ce3 ("anv: Allow PMA optimization to be enabled in secondary command buffers")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Tested-by: Matt Turner <mattst88 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15048>
(cherry picked from commit df0e2a1565587cec47a8074f0d4a597e21e99783)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d25a226fa9adf73655fe4c8e4f3a4cf3e7c331c
Author: Iván Briano <ivan.briano at intel.com>
Date: Tue Feb 15 14:33:28 2022 -0800
intel/compiler: make CLUSTER_BROADCAST always deal with integers
This way we don't run afoul of regioning restrictions around floating
point types.
Cc: 22.0 <mesa-stable>
Reviewed-by: Jason Ekstrand <jason.ekstrand at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15039>
(cherry picked from commit 81f97905c3be29bbe81104ef149b4ee14c015f60)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa4d9f59348a4e426d51dda022b014fa166bbd6d
Author: Iván Briano <ivan.briano at intel.com>
Date: Tue Feb 15 14:30:14 2022 -0800
anv: only advertise 64b atomic floats if 64b floats are supported
Cc: 22.0 <mesa-stable>
Reviewed-by: Jason Ekstrand <jason.ekstrand at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15039>
(cherry picked from commit 11544435ad69ee75039e9685a6e219395c67d7eb)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a03c296fd78fd25bfcf1b02962b8d49bec0e4b6
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Feb 14 10:38:04 2022 +0100
radv: enable radv_disable_aniso_single_level for The Evil Within 1&2
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6033
Fixes: 5ce4017a2bf ("radv,aco: do not disable anisotropy filtering for non-mipmap images")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15011>
(cherry picked from commit 80716b6f7e9fe0c93e6a244d23689b0ff81c2927)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=527bac358d53c4a6426d96ada501fad3fef4b6f5
Author: Dylan Baker <dylan.c.baker at intel.com>
Date: Tue Feb 22 12:08:05 2022 -0800
.pick_status.json: Update to 3759a16d8a883355effa435f46867951ce712dbe
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=277d7fe83d36e608e436fd135a3a53deb265885a
Author: Paulo Zanoni <paulo.r.zanoni at intel.com>
Date: Fri May 21 16:14:02 2021 -0700
iris: handle IRIS_MEMZONE_BINDER with a real vma_heap like the others
We're moving towards a path where all contexts share the same virtual
memory - because this will make implementing vm_bind much easier - ,
and to achieve that we need to rework the binder memzone. As it is,
different contexts will choose overlapping addresses. So in this patch
we adjust the Binder to be 1GB - per Ken's suggestion - and use a real
vma_heap for it. As a bonus the code gets simpler since it just reuses
the same pattern we already have for the other memzones.
Credits to Kenneth Granunke for helping me with this change.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
(cherry picked from commit 70dcffde4e584f326b8ced58986061d824d9f318)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15036>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e76b049b2ba9933b624b31caeaba53c9b498b991
Author: Thierry Reding <treding at nvidia.com>
Date: Wed Oct 6 22:47:17 2021 +0200
tegra: Use private reference count for resources
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on resources can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: 7688b8ae9802 ("st/mesa: eliminate all atomic ops when setting vertex buffers")
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Tested-by: Karol Herbst <kherbst at redhat.com>
(cherry picked from commit 108e6eaa83eed3eb356f3cce835c5f5e3a836b8e)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd23929d016f95f27281a63072a6b8bce7162aa0
Author: Thierry Reding <treding at nvidia.com>
Date: Wed Oct 6 22:42:36 2021 +0200
tegra: Use private reference count for sampler views
With the recent addition of the shortcuts aiming to avoid atomic
operations, the reference count on sampler views can become unbalanced
in the Tegra driver since they are wrapped and then proxied to the
Nouveau driver.
Fix this by keeping a private reference count.
Fixes: ef5d42741327 ("st/mesa: add a mechanism to bypass atomics when binding sampler views")
Reviewed-by: Karol Herbst <kherbst at redhat.com>
Tested-by: Karol Herbst <kherbst at redhat.com>
(cherry picked from commit e8ce0a335704af54b8269d6e862835703700392b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47c9c42764f25eaf11e002c6ec7187508f994429
Author: Timur Kristóf <timur.kristof at gmail.com>
Date: Sat Feb 12 17:27:41 2022 +0100
radv: Disable IB2 on compute queues.
The "IB2" indirect buffer command is not supported on compute queues
according to PAL, and it indeed causes GPU hangs when task shaders are
used together with vkCmdExecuteCommands.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15006>
(cherry picked from commit da719792ad2b7f50824fd1ba500f8b87e4b3b448)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db7f26a94475b01da3896b4ce5403f7d6878e8ae
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Wed Nov 24 17:51:19 2021 +0100
ir3/spill: Fix simplify_phi_nodes with multiple loop nesting
Once we simplified a phi node, we never updated the definition it points
to, which meant that it could become out of date if that definition were
also simplified, and we didn't check that when rewriting sources. That
could happen when there are multiple nested loops with phi nodes at the
header.
Fix it by updating the phi's pointer. Since we always update sources
after visiting the definition it points to, when we go to rewrite a
source, if that source points to a simplified phi, the phi's pointer
can't be pointing to a simplified phi because we already visited the phi
earlier in the pass and updated it, or else it's been simplified in the
meantime and this isn't the last pass. This way we don't need to
keep recursing when rewriting sources.
Fixes: 613eaac7b53 ("ir3: Initial support for spilling non-shared registers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15035>
(cherry picked from commit 3ef858a6f6789207e3f24550e9dfb595e3018029)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d191aa607ce5292623ce8777ddcf001ab95e69f4
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Feb 15 10:22:15 2022 +0200
mesa/st: always use DXT5 when transcoding ASTC format
This fixes artifacts seen in games when using ASTC transcoding,
we need to use DXT5 for proper alpha channel support.
Number of components is a block specific property, there is no easy
way to see if we will require >1bit alpha support or not, so simply
use DXT5 to have support in place.
Fixes: 91cbe8d855c ("gallium: Add a transcode_astc driconf option")
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15029>
(cherry picked from commit d3b4202b63cb3aca42bc91c5bc416acc1b7f382b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9215c391adacc35c42a9172cc109463e13b8f49
Author: Yiwei Zhang <zzyiwei at chromium.org>
Date: Tue Feb 15 20:15:57 2022 +0000
venus: properly destroy deferred ahb image before real image creation
Fixes: 19b7b09885c ("venus: prepare image creation helpers for AHB")
Signed-off-by: Yiwei Zhang <zzyiwei at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15037>
(cherry picked from commit 9dd15295e30b3dd5a75440dab05a1eb4019ef1a8)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53f532bac20b7bd40d8c60225095e98a235cae9a
Author: Emma Anholt <emma at anholt.net>
Date: Sat Feb 5 20:11:25 2022 -0800
i915g: Initialize the rest of the "from_nir" temporary VS struct.
draw looked at the uninitialized XFB state, which should just be zeroed
out since i915 doesn't have XFB.
Fixes: 2b3fc26da8be ("i915g: Switch to using nir-to-tgsi.")
Reviewed-by: Zoltán Böszörményi <zboszor at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14896>
(cherry picked from commit 780949c62bc2cd1805f99911a76fde016e430b6b)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7885a3d1b11961f48242f51879fe8b990e2f6cfb
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Feb 14 07:40:51 2022 +0200
iris: fix a leak on surface states
Cc: mesa-stable
Closes:https://gitlab.freedesktop.org/mesa/mesa/-/issues/6013
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15010>
(cherry picked from commit ecc00410302cae4e22ad7718a531f03658190389)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=081ea7fc89af636cca483014e49fb0f145835cfa
Author: Danylo Piliaiev <dpiliaiev at igalia.com>
Date: Thu Feb 10 14:07:12 2022 +0200
ir3: Limit the maximum imm offset in nir_opt_offset for shared vars
STL/LDL have 13 bits to store imm offset.
Fixes crash in CS compilation in Monster Hunter World.
Fixes: b024102d7c2959451bfef323432beaa4dca4dd88
("freedreno/ir3: Use nir_opt_offset for removing constant adds for shared vars.")
Signed-off-by: Danylo Piliaiev <dpiliaiev at igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14968>
(cherry picked from commit 0b2da9d795610df15346a594384c39a096be338f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc450c2f544056babd4a474e2cd8164e45a78844
Author: Marcin Ślusarz <marcin.slusarz at intel.com>
Date: Fri Feb 11 17:28:35 2022 +0100
intel/compiler: fix array & struct IO lowering in mesh shaders
We really need offsets to be in dwords, not in vec4s.
The bug manifests as random failure of func.mesh.clipdistance.5 crucible
test, where stores to gl_MeshVerticesNV[x].gl_ClipDistance[4+n] actually write to
gl_MeshVerticesNV[x].gl_ClipDistance[1+n].
Fixes: 1f438eb0337 ("intel/compiler: Implement Mesh Output")
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14997>
(cherry picked from commit b6557b80a50aa96ac0862bc029d72625ea4dd6db)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c3a61979b6478e3a7bd17eb2e788bd066551a20
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sat Jan 15 14:43:15 2022 +0100
radv: Fix preamble argument order.
Used the wrong cmdbuffer in the wrong situation. Oops.
Fixes: 915e9178faf ("radv: Split out commandbuffer submission.")
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14574>
(cherry picked from commit 79131b6ee6c98a8b662aeb32bb623a8974f8bef5)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c22f3ffaf654398969695933aeba9a29a19bbbe
Author: Erico Nunes <nunes.erico at gmail.com>
Date: Sat Feb 5 11:14:36 2022 +0100
lima/ppir: refactor bitcopy to use unsigned char
This code does not work as expected when built with clang and
-fstrict-aliasing.
Redefine it in unsigned char operations so that it does not
violate strict aliasing rules.
Signed-off-by: Erico Nunes <nunes.erico at gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul at gmail.com>
Cc: 22.0 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14894>
(cherry picked from commit 0f9756f4808739c8b18e62e28bdbb430af735c67)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=295022cb757e78f8774544a9771d1b784d090ec0
Author: Erico Nunes <nunes.erico at gmail.com>
Date: Wed Feb 2 12:30:56 2022 +0100
lima/ppir: initialize slots array for dummy/undef
Some functions in ppir iterate the ppir_op_info slots arrays looking
for the PPIR_INSTR_SLOT_END token. The dummy/undef internal ops may
appear in the scheduling code and their slots arrays did not contain
that token, which could result in invalid array reads.
Reported by gcc -fsanitize=address.
Signed-off-by: Erico Nunes <nunes.erico at gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul at gmail.com>
Cc: 22.0 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14894>
(cherry picked from commit 7297f931f04bedb2a49a723972e5de8daad7b487)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e7d39f9db9ce102b992759add3c945ec454ed65
Author: Erico Nunes <nunes.erico at gmail.com>
Date: Wed Feb 2 12:27:08 2022 +0100
lima/gpir: avoid invalid write in regalloc
Reported by gcc -fsanitize=address, sometimes gpir regalloc attempts to
handle an uninitialized node->value_reg (containing the value -1), which
results in an invalid array access.
Avoid it for now to prevent crashes, but more investigation may be
required later on.
Signed-off-by: Erico Nunes <nunes.erico at gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul at gmail.com>
Cc: 22.0 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14894>
(cherry picked from commit 5b1584936632f9e7f21cc57746ca51cbdc526b0f)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=95f87609de568cbcfbd98a18a2cde3e144423e45
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Feb 11 11:17:49 2022 +0100
radv/winsys: fix initializing debug/perftest options if multiple instances
Since the winsys uses refcount, options like RADV_DEBUG_ZERO_VRAM might
have not been initialized if the first instance wasn't created with
application info.
This fixes missing zerovram for vkd3d-proton.
Cc: 21.3 22.0 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14978>
(cherry picked from commit aa3405e8123324b3d8173c709e6573d86570d99a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fd825b4f4751825e9a953347d54c2336c3168a5
Author: Dylan Baker <dylan.c.baker at intel.com>
Date: Wed Feb 16 09:13:41 2022 -0800
.pick_status.json: Mark b07372312d7053f2ef5c858ceb1fbf9ade5e7c52 as denominated
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcd93800bb79a8fa32964d001b98c5ac8df3d3b3
Author: Jason Ekstrand <jason.ekstrand at collabora.com>
Date: Tue Feb 8 16:04:34 2022 -0600
anv: Call vk_command_buffer_finish if create fails
This wasn't much of a problem before because vk_command_buffer_finish()
doesn't do much on an empty command buffer. However, it's about to be
responsible for managing the pool's list of command buffers so it will
be critical to get this right.
Fixes: c9189f481353 ("anv: Use a common vk_command_buffer structure")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14917>
(cherry picked from commit 7b0e30685446d30aaea1c2c7c1fd04a658c74d94)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3241c61b682adaf5a061c7ab4fc0eb737b91fa99
Author: Iván Briano <ivan.briano at intel.com>
Date: Thu Feb 10 14:26:21 2022 -0800
anv: make the pointer valid before we assign stuff into it
Fixes: 665ffd4bf9c ("anv: Update VK_KHR_fragment_shading_rate for newer HW")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14982>
(cherry picked from commit e2a5e2d5a0f8ed972a4669be9c5d689a6b3e7bca)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e791cc3ca530669bb2ed0f450417549403b972ed
Author: Dylan Baker <dylan.c.baker at intel.com>
Date: Wed Feb 16 09:13:15 2022 -0800
.pick_status.json: Update to 108e6eaa83eed3eb356f3cce835c5f5e3a836b8e
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21dfddc2f6cd093dd9cfe986c120bb2133da724c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 10:50:55 2021 -0700
nir: Produce correct results for atan with NaN
Properly handling NaN adversely affects several hundred shaders in
shader-db (lots of Skia and a few others from various synthetic
benchmarks) and fossil-db (mostly Talos and some Doom 2016). Only apply
the NaN handling work-around when the shader demands it.
v2: Add comment explaining the 1.0*y_over_x. Suggested by Caio.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 2098ae16c8b ("nir/builder: Move nir_atan and nir_atan2 from SPIR-V translator")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 1cb3d1a6ae027b5045e47ccf7e551bd81fc3cab2)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1830da60e8d2eb753538e0ec733f02857e607450
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 28 17:34:56 2021 -0700
nir: Properly handle various exceptional values in frexp
frexp_sig of ±0, ±Inf, or NaN should just return the input unmodified.
frexp_exp of ±Inf or NaN is undefined, and frexp_exp of ±0 should return
the input unmodified. This seems to already work.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 23d30f4099f ("spirv,nir: lower frexp_exp/frexp_sig inside a new NIR pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 7d0d9b9fbc231c2bd66778e0b0a62d5c514c5495)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea3afa5690953c09467d3f56c429deadc2bbcd47
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 10:51:25 2021 -0700
spirv: Produce correct result for GLSLstd450Tanh with NaN
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 9f9432d56c0 ("Revert "spirv: Use a simpler and more correct implementaiton of tanh()"")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 93ed87af28e7f5b7db7bae095e5a37b63b7bd2c7)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cca40e8a3a0dedf2512db3ae8efb107ed7d4eb4
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 08:15:18 2021 -0700
spirv: Produce correct result for GLSLstd450Modf with Inf
GLSLstd450ModfStruct too.
No shader-db or fossil-db changes on any Intel platform.
v2: Fix handling 16-bit (and presumably 64-bit) values.
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: f92a35d831c ("vtn: Fix Modf.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit e442b9d79296ad9322af61fdadbc81d680466f57)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b73963911f716e333c5807ade72f960881e9151
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 28 17:33:02 2021 -0700
spriv: Produce correct result for GLSLstd450Step with NaN
NOTE: This commit needs "nir: All set-on-comparison opcodes can take all
float types" or regressions will occur in other Vulkan SPIR-V tests.
No shader-db changes on any Intel platform.
NOTE: This commit depends on "nir: All set-on-comparison opcodes can
take all float types".
v2: Fix handling 16-bit (and presumably 64-bit) values.
About 280 shaders in Talos are hurt by a few instructions, and a couple
shaders in Doom 2016 are hurt by a few instructions.
Tiger Lake
Instructions in all programs: 159893290 -> 159895026 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019260087 -> 7019254134 (-0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)
Ice Lake
Instructions in all programs: 143624235 -> 143625691 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440083238 -> 8440090702 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)
Skylake
Instructions in all programs: 134185495 -> 134186618 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366923 -> 8222365826 (-0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: 1feeee9cf47 ("nir/spirv: Add initial support for GLSL 4.50 builtins")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 75ef5991f5af06997551dabc053300261e32ca40)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d4287079824b07f21fc5e1137591a4d87fb408e
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 29 14:16:44 2021 -0700
intel/fs: Don't optimize out 1.0*x and -1.0*x
This (sort of) matches the behavior of nir_opt_algebraic. This ensures
that subnormal values are properly flushed to zero.
With the aid of "nir/search: Float sources of texture instructions are
float users" and "nir/search: Transitively apply is_only_used_as_float",
there would have been no shader-db regressions on Intel platforms.
However, those caused a significant increase in compile time. Since the
instruction regressions were so small, I just dropped those commits
rather than improve them.
All Haswell and newer platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 20125042 -> 20125094 (<.01%)
instructions in affected programs: 7184 -> 7236 (0.72%)
helped: 0
HURT: 32
HURT stats (abs) min: 1 max: 4 x̄: 1.62 x̃: 2
HURT stats (rel) min: 0.11% max: 1.49% x̄: 0.85% x̃: 0.78%
95% mean confidence interval for instructions value: 1.39 1.86
95% mean confidence interval for instructions %-change: 0.74% 0.96%
Instructions are HURT.
total cycles in shared programs: 862745586 -> 862746551 (<.01%)
cycles in affected programs: 109872 -> 110837 (0.88%)
helped: 12
HURT: 23
helped stats (abs) min: 2 max: 774 x̄: 90.83 x̃: 19
helped stats (rel) min: 0.07% max: 25.23% x̄: 3.06% x̃: 0.40%
HURT stats (abs) min: 2 max: 1106 x̄: 89.35 x̃: 12
HURT stats (rel) min: 0.08% max: 45.40% x̄: 3.01% x̃: 0.47%
95% mean confidence interval for cycles value: -60.09 115.23
95% mean confidence interval for cycles %-change: -2.21% 4.07%
Inconclusive result (value mean confidence interval includes 0).
All of the shaders hurt are in either UE4 shooter-game or shooter_demo.
Tiger Lake
Instructions in all programs: 159893213 -> 159893290 (+0.0%)
SENDs in all programs: 6936431 -> 6936431 (+0.0%)
Loops in all programs: 38385 -> 38385 (+0.0%)
Cycles in all programs: 7019259514 -> 7019260087 (+0.0%)
Spills in all programs: 101389 -> 101389 (+0.0%)
Fills in all programs: 131532 -> 131532 (+0.0%)
Ice Lake
Instructions in all programs: 143624164 -> 143624235 (+0.0%)
SENDs in all programs: 6980289 -> 6980289 (+0.0%)
Loops in all programs: 38383 -> 38383 (+0.0%)
Cycles in all programs: 8440082767 -> 8440083238 (+0.0%)
Spills in all programs: 102246 -> 102246 (+0.0%)
Fills in all programs: 131908 -> 131908 (+0.0%)
Skylake
Instructions in all programs: 134185424 -> 134185495 (+0.0%)
SENDs in all programs: 6938790 -> 6938790 (+0.0%)
Loops in all programs: 38356 -> 38356 (+0.0%)
Cycles in all programs: 8222366529 -> 8222366923 (+0.0%)
Spills in all programs: 98821 -> 98821 (+0.0%)
Fills in all programs: 125218 -> 125218 (+0.0%)
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Fixes: f5dd6dfe012 ("anv: enable VK_KHR_shader_float_controls and SPV_KHR_float_controls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 38a94c82e6ac3ae3e76e01ff4994ae4c46c487ec)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc1511acd77492a26bb761f0ef6637e82bc0b0c6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 30 09:45:49 2021 -0800
nir: All set-on-comparison opcodes can take all float types
Extend 4195a9450bde so that the next poor fool doesn't come along and
say, "sge does the right thing for 16-bit sources, but slt gives a NIR
validation failure. What the deuce?"
NOTE: This commit is necessary to prevent regressions in GLSLstd450Step
tests of 16-bit sources at "spriv: Produce correct result for
GLSLstd450Step with NaN".
Fixes: 4195a9450bd ("nir: sge operation is defined for floating-point types")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13999>
(cherry picked from commit 38800b385c6b4752ec1a91db5b8a7de149d03d0c)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a32927b18747c992c5576281d03db9168e813e71
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Dec 27 10:15:19 2021 -0500
iris: Don't fast clear with the view format
Fast clear with the resource format instead. This is safe to do because
can_fast_clear_color ensures that the clear color generates the same
pixel with either the view format or the resource format.
On SKL, this prevents us from using an invalid surface state. This platform
doesn't support CCS_E with sRGB formats, but prior to this patch we allowed
fast-clearing with this combination. Piglit's fcc-write-after-clear test
can trigger this.
Fixes: 230952c2101 ("iris: Don't support sRGB + Y_TILED_CCS on gen9")
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14806>
(cherry picked from commit 6778b3a379d010d9b4d82e7324bff19d73cd3d1a)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=17580829123b09881bc5b56239d3099d01754f2d
Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date: Wed Feb 9 09:07:41 2022 -0500
aux/draw: fix llvm tcs lane vec generation
the idx param for LLVMBuildInsertElement is zero-indexed based on the
value of 'vector_length' (always 4), and the vector length is (obviously)
sized to 'vector_length', so this should be the member of the vec that is being
inserted, not the invocation index
cc: mesa-stable
fixes (zink, but only on my one machine):
KHR-GL46.tessellation_shader.single.max_patch_vertices
KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
dEQP-GLES31.functional.tessellation.shader_input_output.barrier
dEQP-GLES31.functional.tessellation.shader_input_output.patch_vertices_5_in_10_out
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_isolines_point_mode_geometry_output_triangles
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_quads_point_mode_geometry_output_lines
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_geometry_output_points
dEQP-GLES31.functional.tessellation_geometry_interaction.feedback.tessellation_output_triangles_point_mode_geometry_output_lines
Reviewed-by: Dave Airlie <airlied at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14949>
(cherry picked from commit 68c1b50e48e32ec8ff4815666b7124d4cb4171ab)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d653651b49df3b9bf7ab4165cb221a66b7b9bd5c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 8 17:53:02 2022 -0800
gallivm/nir: Call nir_lower_bool_to_int32 after nir_opt_algebraic_late
All of the opcodes in nir_opt_algebraic_late are the unsized (1-bit)
versions. If the lowering to int32 happens first, many of the
optimizations and lowerings won't happen.
Of particular importance is the lowering of fisfinite. If a shader
happens to contain fisfinite of an fp16 value, it will assert later
during compliation.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Fixes: 78b4e417d44 ("gallivm: handle fisfinite/fisnormal")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14942>
(cherry picked from commit e3cbc328e0dbb5865cc036ecbf977127850b4670)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ba68c86f788aff078851cb70d25fa6dc327b7eb
Author: Dylan Baker <dylan.c.baker at intel.com>
Date: Thu Feb 10 12:59:52 2022 -0800
.pick_status.json: Update to 22fc53493092a7507c1e2db47b0c8763158d7b2d
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=166fc8e9f327dcf154a7e840dc66e8d21657377d
Author: Qiang Yu <yuq825 at gmail.com>
Date: Wed Feb 9 09:40:22 2022 +0800
radeonsi: workaround Specviewperf13 Catia hang on GFX9
The root cause is unknown but PAL always update IA_MULTI_VGT_PARAM
whenever primitive type change.
cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Singed-off-by: Qiang Yu <yuq825 at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14944>
(cherry picked from commit fe560aeb12516e766335d416ba749b7572637274)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1822e7222f090a336b03f7403788bc2cac0bc6f
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Feb 6 14:13:24 2022 -0800
intel/fs: Assert that old pull-const code is not used if devinfo->has_lsc
Jason changed this to use LSC in:
f5876dfdb9b ("intel/fs: Lower uniform pull constant load message to LSC dataport")
Cc: 22.0 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14384>
(cherry picked from commit e2cd0c3a3c21d99ad0b99d1e21a8cad148a78aaf)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb8a9be463fd4e8bbe6e9340f4a7e61f97018630
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jan 31 11:52:21 2022 +0200
iris: invalidate L3 read only cache when VF cache is invalidated
When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.
Ref: bspec 46314
Fixes: ed8f2c4cbee ("iris: Cache VB/IB in L3$ for Gen12")
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 562f7eef5b4f5a4d4fb4d93418e6373e853550fa)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0ad08de15ca1fa073f2fb912141bd90715a628b
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jan 31 11:49:53 2022 +0200
anv: invalidate L3 read only cache when VF cache is invalidated
When enabling the caching of index,vertex data in the L3 RO Cache
(L3BypassDisable), we need to use L3ReadOnlyCacheInvalidationEnable
to invalidate cache when buffer is modified by CPU/GPU.
Ref: bspec 46314
Fixes: 6c345ddbe40 ("anv: Cache VB/IB in L3$ for Gfx12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5941
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 7a6ea047954461d8f61878494265ba4bb84b50fe)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c820bbced0bd852ae00e60506164a168e896d078
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jan 31 11:48:49 2022 +0200
intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14815>
(cherry picked from commit 442628b70244f2c9fd0ed79e0656e999ee6fffca)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8e9c345d063c8283be9cb2e625f09e7de7ce47b
Author: Pavel Ondračka <pavel.ondracka at gmail.com>
Date: Mon Feb 7 16:49:38 2022 +0100
r300: fix transformation of abs modifiers with negate
It is being overwritten by the memset. Just set the only remaining
member RelAddr explicitly.
Signed-off-by: Pavel Ondračka <pavel.ondracka at gmail.com>
Reviewed-by: Filip Gawin <filip.gawin at zoho.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14915>
(cherry picked from commit 1f5330de3a6c54faf7a0ed7485c72a2ce40ac744)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b1563dcfb4d2123338fc46a4c2bc1310395baee
Author: Jesse Natalie <jenatali at microsoft.com>
Date: Mon Feb 7 19:03:04 2022 -0800
tc: CPU storage needs to be freed with align_free
Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Reviewed-by: Sil Vilerino <sivileri at microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14933>
(cherry picked from commit 7ec0e2b89351e6e56cb112e00e6c68c6bbc6faea)
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