Mesa (main): freedreno: Replace A6XX_IBO with A6XX_TEX_CONST
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Mon Feb 28 23:55:24 UTC 2022
Module: Mesa
Branch: main
Commit: 00be8c46197f53a63e3683a28423a34db8ed765b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=00be8c46197f53a63e3683a28423a34db8ed765b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Mon Feb 21 19:05:52 2022 +0100
freedreno: Replace A6XX_IBO with A6XX_TEX_CONST
Since these were reverse-engineered, it's become clear that IBO
descriptors are just a subset of texture descriptors, and bindless reads
of readonly images actually use isam on the IBO descriptor, further
confirming that the two are always compatible, even if not all of the
texture fields exist for IBOs. It's pointless to have a separate type
for IBOs, and just leads to things getting out-of-sync unnecessarily
which has already happened. Just remove it and use TEX_CONST insted.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>
---
src/freedreno/computerator/a6xx.c | 10 ++---
src/freedreno/decode/cffdec.c | 2 +-
src/freedreno/fdl/fd6_view.c | 28 +++++---------
src/freedreno/registers/adreno/a6xx.xml | 65 --------------------------------
src/freedreno/vulkan/tu_cmd_buffer.c | 2 +-
src/freedreno/vulkan/tu_descriptor_set.c | 10 ++---
6 files changed, 21 insertions(+), 96 deletions(-)
diff --git a/src/freedreno/computerator/a6xx.c b/src/freedreno/computerator/a6xx.c
index 64d79b2c4e6..cd7e61309ab 100644
--- a/src/freedreno/computerator/a6xx.c
+++ b/src/freedreno/computerator/a6xx.c
@@ -314,11 +314,11 @@ cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
unsigned width = sz & MASK(15);
unsigned height = sz >> 15;
- OUT_RING(state, A6XX_IBO_0_FMT(FMT6_32_UINT) | A6XX_IBO_0_TILE_MODE(0));
- OUT_RING(state, A6XX_IBO_1_WIDTH(width) | A6XX_IBO_1_HEIGHT(height));
- OUT_RING(state, A6XX_IBO_2_PITCH(0) | A6XX_IBO_2_UNK4 | A6XX_IBO_2_UNK31 |
- A6XX_IBO_2_TYPE(A6XX_TEX_1D));
- OUT_RING(state, A6XX_IBO_3_ARRAY_PITCH(0));
+ OUT_RING(state, A6XX_TEX_CONST_0_FMT(FMT6_32_UINT) | A6XX_TEX_CONST_0_TILE_MODE(0));
+ OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(width) | A6XX_TEX_CONST_1_HEIGHT(height));
+ OUT_RING(state, A6XX_TEX_CONST_2_PITCH(0) | A6XX_TEX_CONST_2_BUFFER |
+ A6XX_TEX_CONST_2_TYPE(A6XX_TEX_BUFFER));
+ OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(0));
OUT_RELOC(state, kernel->bufs[i], 0, 0, 0);
OUT_RING(state, 0x00000000);
OUT_RING(state, 0x00000000);
diff --git a/src/freedreno/decode/cffdec.c b/src/freedreno/decode/cffdec.c
index 0c4dc1e905b..9c9ccc23913 100644
--- a/src/freedreno/decode/cffdec.c
+++ b/src/freedreno/decode/cffdec.c
@@ -1570,7 +1570,7 @@ cp_load_state(uint32_t *dwords, uint32_t sizedwords, int level)
dump_domain(ssboconst, 4, level + 2, "A5XX_SSBO_0");
} else if (600 <= options->gpu_id && options->gpu_id < 700) {
sz = 16;
- dump_domain(ssboconst, 16, level + 2, "A6XX_IBO");
+ dump_domain(ssboconst, 16, level + 2, "A6XX_TEX_CONST");
}
dump_hex(ssboconst, sz, level + 1);
ssboconst += sz;
diff --git a/src/freedreno/fdl/fd6_view.c b/src/freedreno/fdl/fd6_view.c
index 0f99dd0bb77..cacb90443d3 100644
--- a/src/freedreno/fdl/fd6_view.c
+++ b/src/freedreno/fdl/fd6_view.c
@@ -340,27 +340,17 @@ fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
memset(view->storage_descriptor, 0, sizeof(view->storage_descriptor));
view->storage_descriptor[0] =
- A6XX_IBO_0_FMT(storage_format) |
- A6XX_IBO_0_TILE_MODE(tile_mode);
- view->storage_descriptor[1] =
- A6XX_IBO_1_WIDTH(width) |
- A6XX_IBO_1_HEIGHT(height);
+ A6XX_TEX_CONST_0_FMT(storage_format) |
+ A6XX_TEX_CONST_0_TILE_MODE(tile_mode);
+ view->storage_descriptor[1] = view->descriptor[1];
view->storage_descriptor[2] =
- A6XX_IBO_2_PITCH(pitch) |
- A6XX_IBO_2_TYPE(fdl6_tex_type(args->type, true));
- view->storage_descriptor[3] = A6XX_IBO_3_ARRAY_PITCH(layer_size);
-
+ A6XX_TEX_CONST_2_PITCH(pitch) |
+ A6XX_TEX_CONST_2_TYPE(fdl6_tex_type(args->type, true));
+ view->storage_descriptor[3] = view->descriptor[3];
view->storage_descriptor[4] = base_addr;
- view->storage_descriptor[5] = (base_addr >> 32) | A6XX_IBO_5_DEPTH(storage_depth);
-
- if (ubwc_enabled) {
- view->storage_descriptor[3] |= A6XX_IBO_3_FLAG | A6XX_IBO_3_UNK27;
- view->storage_descriptor[7] |= ubwc_addr;
- view->storage_descriptor[8] |= ubwc_addr >> 32;
- view->storage_descriptor[9] = A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2);
- view->storage_descriptor[10] =
- A6XX_IBO_10_FLAG_BUFFER_PITCH(ubwc_pitch);
- }
+ view->storage_descriptor[5] = (base_addr >> 32) | A6XX_TEX_CONST_5_DEPTH(storage_depth);
+ for (unsigned i = 6; i <= 10; i++)
+ view->storage_descriptor[i] = view->descriptor[i];
view->width = width;
view->height = height;
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index c9e1b77d43c..2bf482fd316 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -3882,71 +3882,6 @@ to upconvert to 32b float internally?
<reg32 offset="15" name="15"/>
</domain>
-<!--
-Note the "SSBO" state blocks are actually used for both images and SSBOs,
-naming is just because I r/e'd SSBOs first. I should probably come up
-with a better name.
--->
-<domain name="A6XX_IBO" width="32">
- <reg32 offset="0" name="0">
- <!--
- NOTE: same position as in TEX_CONST state.. I don't see other bits
- used but if they are good chance position is same as TEX_CONST
- -->
- <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
- <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
- </reg32>
- <reg32 offset="1" name="1">
- <bitfield name="WIDTH" low="0" high="14" type="uint"/>
- <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
- </reg32>
- <reg32 offset="2" name="2">
- <!--
- b4 and b31 set for buffer/ssbo case, in which case low 15 bits
- of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
- -->
- <bitfield name="UNK4" pos="4" type="boolean"/>
- <doc>Pitch in bytes (so actually stride)</doc>
- <bitfield name="PITCH" low="7" high="28" type="uint"/>
- <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
- <bitfield name="UNK31" pos="31" type="boolean"/>
- </reg32>
- <reg32 offset="3" name="3">
- <!--
- ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
- for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
- layer size at the point that it stops being reduced moving to
- higher (smaller) mipmap levels
- -->
- <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
- <bitfield name="UNK27" pos="27" type="boolean"/>
- <bitfield name="FLAG" pos="28" type="boolean"/>
- </reg32>
- <reg32 offset="4" name="4">
- <bitfield name="BASE_LO" low="0" high="31"/>
- </reg32>
- <reg32 offset="5" name="5">
- <bitfield name="BASE_HI" low="0" high="16"/>
- <bitfield name="DEPTH" low="17" high="29" type="uint"/>
- </reg32>
- <reg32 offset="6" name="6">
- </reg32>
- <reg32 offset="7" name="7">
- </reg32>
- <reg32 offset="8" name="8">
- </reg32>
- <reg32 offset="9" name="9">
- <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
- </reg32>
- <reg32 offset="10" name="10">
- <!--
- I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
- don't seem to be particularly sensible... or needed for UBWC to work
- -->
- <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
- </reg32>
-</domain>
-
<domain name="A6XX_UBO" width="32">
<reg32 offset="0" name="0">
<bitfield name="BASE_LO" low="0" high="31"/>
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index f6dc6ea39fd..cac97fcc350 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -1893,7 +1893,7 @@ tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer,
dst[1] = va >> 32;
} else {
memcpy(dst, src, A6XX_TEX_CONST_DWORDS * 4);
- /* Note: A6XX_IBO_5_DEPTH is always 0 */
+ /* Note: A6XX_TEX_CONST_5_DEPTH is always 0 */
uint64_t va = dst[4] | ((uint64_t)dst[5] << 32);
va += offset;
dst[4] = va;
diff --git a/src/freedreno/vulkan/tu_descriptor_set.c b/src/freedreno/vulkan/tu_descriptor_set.c
index 97142a6d59e..c081866c50c 100644
--- a/src/freedreno/vulkan/tu_descriptor_set.c
+++ b/src/freedreno/vulkan/tu_descriptor_set.c
@@ -863,17 +863,17 @@ write_buffer_descriptor(const struct tu_device *device,
/* newer a6xx allows using 16-bit descriptor for both 16-bit and 32-bit access */
if (device->physical_device->info->a6xx.storage_16bit) {
- dst[0] = A6XX_IBO_0_TILE_MODE(TILE6_LINEAR) | A6XX_IBO_0_FMT(FMT6_16_UINT);
+ dst[0] = A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR) | A6XX_TEX_CONST_0_FMT(FMT6_16_UINT);
dst[1] = DIV_ROUND_UP(range, 2);
} else {
- dst[0] = A6XX_IBO_0_TILE_MODE(TILE6_LINEAR) | A6XX_IBO_0_FMT(FMT6_32_UINT);
+ dst[0] = A6XX_TEX_CONST_0_TILE_MODE(TILE6_LINEAR) | A6XX_TEX_CONST_0_FMT(FMT6_32_UINT);
dst[1] = DIV_ROUND_UP(range, 4);
}
dst[2] =
- A6XX_IBO_2_UNK4 | A6XX_IBO_2_TYPE(A6XX_TEX_1D) | A6XX_IBO_2_UNK31;
+ A6XX_TEX_CONST_2_BUFFER | A6XX_TEX_CONST_2_TYPE(A6XX_TEX_BUFFER);
dst[3] = 0;
- dst[4] = A6XX_IBO_4_BASE_LO(va);
- dst[5] = A6XX_IBO_5_BASE_HI(va >> 32);
+ dst[4] = A6XX_TEX_CONST_4_BASE_LO(va);
+ dst[5] = A6XX_TEX_CONST_5_BASE_HI(va >> 32);
for (int i = 6; i < A6XX_TEX_CONST_DWORDS; i++)
dst[i] = 0;
}
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