Mesa (main): anv: Add another case to INTEL_DEBUG=pc output

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Module: Mesa
Branch: main
Commit: 9ba7bc17d341e0351bc975589eab6e9f42765f6e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ba7bc17d341e0351bc975589eab6e9f42765f6e

Author: Caio Oliveira <caio.oliveira at intel.com>
Date:   Thu Dec 23 23:14:32 2021 -0800

anv: Add another case to INTEL_DEBUG=pc output

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14301>

---

 src/intel/vulkan/genX_cmd_buffer.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 8c40ba19b50..1245b3ce9a1 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -61,6 +61,7 @@ convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
    bits |= (pc->HDCPipelineFlushEnable) ?  ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
 #endif
    bits |= (pc->RenderTargetCacheFlushEnable) ?  ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT : 0;
+   bits |= (pc->VFCacheInvalidationEnable) ?  ANV_PIPE_VF_CACHE_INVALIDATE_BIT : 0;
    bits |= (pc->StateCacheInvalidationEnable) ?  ANV_PIPE_STATE_CACHE_INVALIDATE_BIT : 0;
    bits |= (pc->ConstantCacheInvalidationEnable) ?  ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT : 0;
    bits |= (pc->TextureCacheInvalidationEnable) ?  ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT : 0;