Mesa (main): ir3: Bump type mismatch penalty to 3
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Fri Jan 7 15:02:56 UTC 2022
Module: Mesa
Branch: main
Commit: 603791bdebda8d8e316fa18e12d72a6a16629825
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=603791bdebda8d8e316fa18e12d72a6a16629825
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Jan 6 20:16:44 2022 +0100
ir3: Bump type mismatch penalty to 3
After some experimentation with computerator, it seems on a618 that
writing a full register and then reading half of it as a half register
requires a delay of 6, the same as the delay for cat5/cat6 sources. The
other direction only has a delay of 5, but just bump it unconditionally
out of an abundance of caution.
Fixes: 890de1a4360 ("ir3/delay: Fix full->half and half->full delay")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14246>
---
src/freedreno/ir3/ir3_delay.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/freedreno/ir3/ir3_delay.c b/src/freedreno/ir3/ir3_delay.c
index bc5ad6d9508..71617aee90f 100644
--- a/src/freedreno/ir3/ir3_delay.c
+++ b/src/freedreno/ir3/ir3_delay.c
@@ -98,7 +98,7 @@ ir3_delayslots(struct ir3_instruction *assigner,
*/
bool mismatched_half = (assigner->dsts[0]->flags & IR3_REG_HALF) !=
(consumer->srcs[n]->flags & IR3_REG_HALF);
- unsigned penalty = mismatched_half ? 2 : 0;
+ unsigned penalty = mismatched_half ? 3 : 0;
if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) && (n == 2)) {
/* special case, 3rd src to cat3 not required on first cycle */
return 1 + penalty;
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