Mesa (main): intel/xehp: Implement XeHP workaround Wa_14014148106.

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Module: Mesa
Branch: main
Commit: 8e21cad39b50fe6bad2ebdc8cf6d4d83f6937dd6
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e21cad39b50fe6bad2ebdc8cf6d4d83f6937dd6

Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Jun 18 19:40:10 2021 -0700

intel/xehp: Implement XeHP workaround Wa_14014148106.

Actually, no, there's no need to do anything, just update some
comments for the record.  An earlier revision of this change that
implemented the workaround text to the letter required no less than 8
new PIPE_CONTROLs throughout the tree.  However Felix Degrood noticed
that the cost of some of the PIPE_CONTROLs was showing up in workloads
like Shadow of the Tomb Raider.  The Windows driver wasn't emitting
many of those pipe controls, contrary to the W/A instructions, so we
engaged in a back and forth with the hardware team, who concluded that
the original suggested workaround was unnecessarily strict, and the
Windows driver's behavior acceptable.  It turns out that Wa_1408224581
we had already implemented for TGL is roughly equivalent to the
Windows behavior, so no need to do anything new after all.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rohan Garg <rohan.garg at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14278>

---

 src/gallium/drivers/iris/iris_state.c | 2 ++
 src/intel/blorp/blorp_genX_exec.h     | 2 ++
 src/intel/vulkan/genX_cmd_buffer.c    | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index f4e18db5a21..9ea435e2074 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -6375,6 +6375,8 @@ iris_upload_dirty_render_state(struct iris_context *ice,
           * post-sync = store dword operation would be required.( w/a is to
           * have an additional pipe control after the stencil state whenever
           * the surface state bits of this state is changing).
+          *
+          * This also seems sufficient to handle Wa_14014148106.
           */
          iris_emit_pipe_control_write(batch, "WA for stencil state",
                                       PIPE_CONTROL_WRITE_IMMEDIATE,
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 64d653884e5..6f43a88334d 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1754,6 +1754,8 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
     * post-sync = store dword operation would be required.( w/a is to
     * have an additional pipe control after the stencil state whenever
     * the surface state bits of this state is changing).
+    *
+    * This also seems sufficient to handle Wa_14014148106.
     */
    blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
       pc.PostSyncOperation = WriteImmediateData;
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index a74ff8229b8..34a4375c4cb 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -5902,6 +5902,8 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
        * post-sync = store dword operation would be required.( w/a is to
        * have an additional pipe control after the stencil state whenever
        * the surface state bits of this state is changing).
+       *
+       * This also seems sufficient to handle Wa_14014148106.
        */
       anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
          pc.PostSyncOperation = WriteImmediateData;