Mesa (main): intel/fs: Don't assume packed dispatch for fragment shaders on XeHP.

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Module: Mesa
Branch: main
Commit: c6455cfec9a6b64d84dfe2e93523f02529628a62
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6455cfec9a6b64d84dfe2e93523f02529628a62

Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sat Oct 16 14:33:51 2021 -0700

intel/fs: Don't assume packed dispatch for fragment shaders on XeHP.

The current packed dispatch assumptions for fragment shaders seem to
be the reason that the fs-readFirstInvocation-uint-loop Piglit
test-case for the ARB_shader_ballot extension fails on DG2 in
combination with the patches in this series that enable pixel pipe
hashing (thanks Jordan for reporting the regression).  I've confirmed
that the brw_fs_test_dispatch_packing() test fails on DG2 hardware for
fragment shaders, while it succeeds for other shader stages,
indicating that the PSD hardware no longer guarantees packed dispatch.
Disable it.

Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>

---

 src/intel/compiler/brw_compiler.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index ac102553935..76f339e7d44 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1945,7 +1945,7 @@ brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo,
        */
       const struct brw_wm_prog_data *wm_prog_data =
          (const struct brw_wm_prog_data *)prog_data;
-      return !wm_prog_data->persample_dispatch;
+      return devinfo->verx10 < 125 && !wm_prog_data->persample_dispatch;
    }
    case MESA_SHADER_COMPUTE:
       /* Compute shaders will be spawned with either a fully enabled dispatch