Mesa (main): anv,iris: Flush tile cache after color fast clears

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Module: Mesa
Branch: main
Commit: 34c8371e2a9e18e21b4828adc18ef51461d3c6e4
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=34c8371e2a9e18e21b4828adc18ef51461d3c6e4

Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Fri Oct  8 10:48:08 2021 -0700

anv,iris: Flush tile cache after color fast clears

Needed for TGL (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rohan Garg <rohan.garg at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>

---

 src/gallium/drivers/iris/iris_clear.c | 5 ++++-
 src/intel/vulkan/anv_blorp.c          | 6 ++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c
index d813eeed6e4..8b663850e30 100644
--- a/src/gallium/drivers/iris/iris_clear.c
+++ b/src/gallium/drivers/iris/iris_clear.c
@@ -169,6 +169,7 @@ fast_clear_color(struct iris_context *ice,
                  union isl_color_value color)
 {
    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
+   const struct intel_device_info *devinfo = &batch->screen->devinfo;
    struct pipe_resource *p_res = (void *) res;
 
    bool color_changed = res->aux.clear_color_unknown ||
@@ -281,7 +282,9 @@ fast_clear_color(struct iris_context *ice,
    blorp_batch_finish(&blorp_batch);
    iris_emit_end_of_pipe_sync(batch,
                               "fast clear: post flush",
-                              PIPE_CONTROL_RENDER_TARGET_FLUSH);
+                              PIPE_CONTROL_RENDER_TARGET_FLUSH |
+                              (devinfo->verx10 == 120 ?
+                                 PIPE_CONTROL_TILE_CACHE_FLUSH : 0));
    iris_batch_sync_region_end(batch);
 
    iris_resource_set_aux_state(ice, res, level, box->z,
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index d290df9dc51..00392f77e56 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1841,6 +1841,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
    /* Multisampling with multi-planar formats is not supported */
    assert(image->n_planes == 1);
 
+   const struct intel_device_info *devinfo = &cmd_buffer->device->info;
    struct blorp_batch batch;
    anv_blorp_batch_init(cmd_buffer, &batch,
                         BLORP_BATCH_PREDICATE_ENABLE * predicate +
@@ -1898,6 +1899,8 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
 
    anv_add_pending_pipe_bits(cmd_buffer,
                              ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+                             (devinfo->verx10 == 120 ?
+                                ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0) |
                              ANV_PIPE_END_OF_PIPE_SYNC_BIT,
                              "after fast clear mcs");
 
@@ -1922,6 +1925,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
           anv_image_aux_layers(image, aspect, level));
 
    const uint32_t plane = anv_image_aspect_to_plane(image, aspect);
+   const struct intel_device_info *devinfo = &cmd_buffer->device->info;
 
    struct blorp_batch batch;
    anv_blorp_batch_init(cmd_buffer, &batch,
@@ -1989,6 +1993,8 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
 
    anv_add_pending_pipe_bits(cmd_buffer,
                              ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+                             (devinfo->verx10 == 120 ?
+                                ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0) |
                              ANV_PIPE_END_OF_PIPE_SYNC_BIT,
                              "after fast clear ccs");