Mesa (main): genxml: reduce amount of generated code

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 51f6288a2d2fa78e723b99a90133f5ebd782bc4a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=51f6288a2d2fa78e723b99a90133f5ebd782bc4a

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Sat Jan  8 13:52:27 2022 +0200

genxml: reduce amount of generated code

$ wc -l build/src/intel/genxml/genX_bits.h

250581 build/src/intel/genxml/genX_bits.h (before)
5748 build/src/intel/genxml/genX_bits.h   (after)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Dave Airlie <airlied at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14469>

---

 src/intel/genxml/gen_bits_header.py | 24 +++++++++++++++++++++---
 src/intel/genxml/meson.build        | 33 ++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py b/src/intel/genxml/gen_bits_header.py
index f70b97ad9c3..f6ddc569ce1 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -104,20 +104,23 @@ ${item.token_name}_${prop}(const struct intel_device_info *devinfo)
 extern "C" {
 #endif
 % for _, container in sorted(containers.items(), key=itemgetter(0)):
+%  if container.allowed:
 
 /* ${container.name} */
 
 ${emit_per_gen_prop_func(container, 'length', True)}
 
-% for _, field in sorted(container.fields.items(), key=itemgetter(0)):
+%   for _, field in sorted(container.fields.items(), key=itemgetter(0)):
+%    if field.allowed:
 
 /* ${container.name}::${field.name} */
 
 ${emit_per_gen_prop_func(field, 'bits', False)}
 
 ${emit_per_gen_prop_func(field, 'start', False)}
-
-% endfor
+%    endif
+%   endfor
+%  endif
 % endfor
 
 #ifdef __cplusplus
@@ -159,6 +162,7 @@ class Container(object):
         self.token_name = safe_name(name)
         self.length_by_gen = {}
         self.fields = {}
+        self.allowed = False
 
     def add_gen(self, gen, xml_attrs):
         assert isinstance(gen, Gen)
@@ -202,6 +206,7 @@ class Field(object):
         self.token_name = safe_name('_'.join([container.name, self.name]))
         self.bits_by_gen = {}
         self.start_by_gen = {}
+        self.allowed = False
 
     def add_gen(self, gen, xml_attrs):
         assert isinstance(gen, Gen)
@@ -299,6 +304,9 @@ def parse_args():
                    help='If unset, then CPP_GUARD is derived from OUTPUT.')
     p.add_argument('--engines', nargs='?', type=str, default='render',
                    help="Comma-separated list of engines whose instructions should be parsed (default: %(default)s)")
+    p.add_argument('--include-symbols', type=str, action='store',
+                   help='List of instruction/structures to generate',
+                   required=True)
     p.add_argument('xml_sources', metavar='XML_SOURCE', nargs='+')
 
     pargs = p.parse_args()
@@ -330,6 +338,16 @@ def main():
         p.engines = set(engines)
         p.parse(source)
 
+    included_symbols_list = pargs.include_symbols.split(',')
+    for _name_field in included_symbols_list:
+        name_field = _name_field.split('::')
+        container = containers[name_field[0]]
+        container.allowed = True
+        if len(name_field) > 1:
+            field = container.get_field(name_field[1])
+            assert field
+            field.allowed = True
+
     with open(pargs.output, 'w') as f:
         f.write(TEMPLATE.render(containers=containers, guard=pargs.cpp_guard))
 
diff --git a/src/intel/genxml/meson.build b/src/intel/genxml/meson.build
index d351f1900aa..4202c138a36 100644
--- a/src/intel/genxml/meson.build
+++ b/src/intel/genxml/meson.build
@@ -40,11 +40,42 @@ genX_xml_h = custom_target(
   capture : true,
 )
 
+genX_bits_included_symbols = [
+  # instructions
+  'MI_BATCH_BUFFER_START::Batch Buffer Start Address',
+  'MI_REPORT_PERF_COUNT::Memory Address',
+  'MI_STORE_DATA_IMM::Address',
+  'MI_STORE_DATA_IMM::Immediate Data',
+  'MI_STORE_REGISTER_MEM::Memory Address',
+  '3DSTATE_DEPTH_BUFFER::Surface Base Address',
+  '3DSTATE_DEPTH_BUFFER::Surface Pitch',
+  '3DSTATE_STENCIL_BUFFER::Surface Base Address',
+  '3DSTATE_STENCIL_BUFFER::Surface Pitch',
+  '3DSTATE_HIER_DEPTH_BUFFER::Surface Base Address',
+  '3DSTATE_HIER_DEPTH_BUFFER::Surface Pitch',
+  '3DSTATE_CLEAR_PARAMS',
+  '3DSTATE_SO_BUFFER::Surface Base Address',
+  '3DSTATE_SO_BUFFER::Stream Offset',
+  # structures
+  'RENDER_SURFACE_STATE::Surface Base Address',
+  'RENDER_SURFACE_STATE::Surface Pitch',
+  'RENDER_SURFACE_STATE::Auxiliary Surface Base Address',
+  'RENDER_SURFACE_STATE::Auxiliary Surface Pitch',
+  'RENDER_SURFACE_STATE::Clear Value Address',
+  'RENDER_SURFACE_STATE::Red Clear Color',
+  'RENDER_SURFACE_STATE::Green Clear Color',
+  'RENDER_SURFACE_STATE::Blue Clear Color',
+  'RENDER_SURFACE_STATE::Alpha Clear Color',
+  'CLEAR_COLOR',
+  'VERTEX_BUFFER_STATE::Buffer Starting Address',
+]
+
 genX_bits_h = custom_target(
   'genX_bits.h',
   input : ['gen_bits_header.py', gen_xml_files],
   output : 'genX_bits.h',
-  command : [prog_python, '@INPUT@', '-o', '@OUTPUT@'],
+  command : [prog_python, '@INPUT@', '-o', '@OUTPUT@',
+             '--include-symbols', ','.join(genX_bits_included_symbols)],
 )
 
 gen_xml_pack = []