Mesa (main): intel/compiler: Move opcode_desc handling to a separate header
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Fri Jul 1 00:15:51 UTC 2022
Module: Mesa
Branch: main
Commit: 342471e93dbb8335970a0ab97aef4d552238b2d3
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=342471e93dbb8335970a0ab97aef4d552238b2d3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jun 29 14:25:19 2022 -0700
intel/compiler: Move opcode_desc handling to a separate header
This patch creates a new header file, brw_isa_info.h, which will
contains all the functions related to opcode encoding on various
generations. Opcode numbers may have different meanings on different
hardware, so we remap them between an enum we can easily work with
and the hardware encoding.
We move the brw_inst setters and getters to brw_inst.h.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>
---
src/intel/compiler/brw_eu.h | 49 +--------------------------
src/intel/compiler/brw_inst.h | 15 +++++++++
src/intel/compiler/brw_isa_info.h | 71 +++++++++++++++++++++++++++++++++++++++
src/intel/compiler/meson.build | 1 +
4 files changed, 88 insertions(+), 48 deletions(-)
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 0ff01a50595..979ed4b8403 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -38,6 +38,7 @@
#include "brw_inst.h"
#include "brw_compiler.h"
#include "brw_eu_defines.h"
+#include "brw_isa_info.h"
#include "brw_reg.h"
#include "brw_disasm_info.h"
@@ -1897,54 +1898,6 @@ next_offset(const struct intel_device_info *devinfo, void *store, int offset)
return offset + 16;
}
-struct opcode_desc {
- unsigned ir;
- unsigned hw;
- const char *name;
- int nsrc;
- int ndst;
- int gfx_vers;
-};
-
-const struct opcode_desc *
-brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode);
-
-const struct opcode_desc *
-brw_opcode_desc_from_hw(const struct intel_device_info *devinfo, unsigned hw);
-
-static inline unsigned
-brw_opcode_encode(const struct intel_device_info *devinfo, enum opcode opcode)
-{
- return brw_opcode_desc(devinfo, opcode)->hw;
-}
-
-static inline enum opcode
-brw_opcode_decode(const struct intel_device_info *devinfo, unsigned hw)
-{
- const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
- return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
-}
-
-static inline void
-brw_inst_set_opcode(const struct intel_device_info *devinfo,
- brw_inst *inst, enum opcode opcode)
-{
- brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
-}
-
-static inline enum opcode
-brw_inst_opcode(const struct intel_device_info *devinfo, const brw_inst *inst)
-{
- return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
-}
-
-static inline bool
-is_3src(const struct intel_device_info *devinfo, enum opcode opcode)
-{
- const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
- return desc && desc->nsrc == 3;
-}
-
/** Maximum SEND message length */
#define BRW_MAX_MSG_LENGTH 15
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 5b531f4f805..0e5cee7c42e 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -35,6 +35,7 @@
#include <stdint.h>
#include "brw_eu_defines.h"
+#include "brw_isa_info.h"
#include "brw_reg_type.h"
#include "dev/intel_device_info.h"
@@ -1444,6 +1445,20 @@ FC(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0, devinfo->ver >= 8)
#undef F
+static inline void
+brw_inst_set_opcode(const struct intel_device_info *devinfo,
+ struct brw_inst *inst, enum opcode opcode)
+{
+ brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
+}
+
+static inline enum opcode
+brw_inst_opcode(const struct intel_device_info *devinfo,
+ const struct brw_inst *inst)
+{
+ return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/src/intel/compiler/brw_isa_info.h b/src/intel/compiler/brw_isa_info.h
new file mode 100644
index 00000000000..f04ceab40ad
--- /dev/null
+++ b/src/intel/compiler/brw_isa_info.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef BRW_ISA_ENCODING_H
+#define BRW_ISA_ENCODING_H
+
+#include "dev/intel_device_info.h"
+#include "brw_eu_defines.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct opcode_desc {
+ unsigned ir;
+ unsigned hw;
+ const char *name;
+ int nsrc;
+ int ndst;
+ int gfx_vers;
+};
+
+const struct opcode_desc *
+brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode);
+
+const struct opcode_desc *
+brw_opcode_desc_from_hw(const struct intel_device_info *devinfo, unsigned hw);
+
+static inline unsigned
+brw_opcode_encode(const struct intel_device_info *devinfo, enum opcode opcode)
+{
+ return brw_opcode_desc(devinfo, opcode)->hw;
+}
+
+static inline enum opcode
+brw_opcode_decode(const struct intel_device_info *devinfo, unsigned hw)
+{
+ const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
+ return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
+}
+
+static inline bool
+is_3src(const struct intel_device_info *devinfo, enum opcode opcode)
+{
+ const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
+ return desc && desc->nsrc == 3;
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build
index e1bfc417d27..10fbb281876 100644
--- a/src/intel/compiler/meson.build
+++ b/src/intel/compiler/meson.build
@@ -76,6 +76,7 @@ libintel_compiler_files = files(
'brw_ir_performance.h',
'brw_ir_performance.cpp',
'brw_ir_vec4.h',
+ 'brw_isa_info.h',
'brw_kernel.c',
'brw_mesh.cpp',
'brw_nir.h',
More information about the mesa-commit
mailing list