Mesa (main): freedreno/registers: add a7xx registers for drm/msm kernel driver
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Fri Jul 1 15:45:44 UTC 2022
Module: Mesa
Branch: main
Commit: de8c769d1168e842f3972bbffed10e2faefe318f
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de8c769d1168e842f3972bbffed10e2faefe318f
Author: Jonathan Marek <jonathan at marek.ca>
Date: Sun Mar 27 16:20:37 2022 -0400
freedreno/registers: add a7xx registers for drm/msm kernel driver
Most of this is taken directly from the downstream kernel driver.
Signed-off-by: Jonathan Marek <jonathan at marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15602>
---
src/freedreno/registers/adreno.xml | 1 +
src/freedreno/registers/adreno/a7xx.xml | 346 +++++++++++++++++++++++
src/freedreno/registers/adreno/adreno_common.xml | 1 +
src/freedreno/registers/adreno/adreno_pm4.xml | 32 +++
4 files changed, 380 insertions(+)
diff --git a/src/freedreno/registers/adreno.xml b/src/freedreno/registers/adreno.xml
index 92b7f37a721..7df6db4a5d3 100644
--- a/src/freedreno/registers/adreno.xml
+++ b/src/freedreno/registers/adreno.xml
@@ -10,6 +10,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="adreno/a5xx.xml"/>
<import file="adreno/a6xx.xml"/>
<import file="adreno/a6xx_gmu.xml"/>
+<import file="adreno/a7xx.xml"/>
<import file="adreno/ocmem.xml"/>
<import file="adreno/adreno_control_regs.xml"/>
<import file="adreno/adreno_pipe_regs.xml"/>
diff --git a/src/freedreno/registers/adreno/a7xx.xml b/src/freedreno/registers/adreno/a7xx.xml
new file mode 100644
index 00000000000..f258f6467bb
--- /dev/null
+++ b/src/freedreno/registers/adreno/a7xx.xml
@@ -0,0 +1,346 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+<domain name="A7XX" width="32">
+ <reg32 offset="0x0011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
+ <reg32 offset="0x0016" name="RBBM_GBIF_HALT"/>
+ <reg32 offset="0x0017" name="RBBM_GBIF_HALT_ACK"/>
+ <reg32 offset="0x001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
+ <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
+ <reg32 offset="0x0038" name="RBBM_INT_0_MASK">
+ <bitfield name="GPUIDLE" pos="0" type="boolean"/>
+ <bitfield name="AHBERROR" pos="1" type="boolean"/>
+ <bitfield name="CPIPCINT0" pos="4" type="boolean"/>
+ <bitfield name="CPIPCINT1" pos="5" type="boolean"/>
+ <bitfield name="ATBASYNCFIFOOVERFLOW" pos="6" type="boolean"/>
+ <bitfield name="GPCERROR" pos="7" type="boolean"/>
+ <bitfield name="SWINTERRUPT" pos="8" type="boolean"/>
+ <bitfield name="HWERROR" pos="9" type="boolean"/>
+ <bitfield name="CCU_CLEAN_DEPTH_TS" pos="10" type="boolean"/>
+ <bitfield name="CCU_CLEAN_COLOR_TS" pos="11" type="boolean"/>
+ <bitfield name="CCU_RESOLVE_CLEAN_TS" pos="12" type="boolean"/>
+ <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean"/>
+ <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean"/>
+ <bitfield name="RB_DONE_TS" pos="17" type="boolean"/>
+ <bitfield name="CACHE_CLEAN_TS" pos="20" type="boolean"/>
+ <bitfield name="CACHE_CLEAN_TS_LPAC" pos="21" type="boolean"/>
+ <bitfield name="ATBBUSOVERFLOW" pos="22" type="boolean"/>
+ <bitfield name="HANGDETECTINTERRUPT" pos="23" type="boolean"/>
+ <bitfield name="OUTOFBOUNDACCESS" pos="24" type="boolean"/>
+ <bitfield name="UCHETRAPINTERRUPT" pos="25" type="boolean"/>
+ <bitfield name="DEBUGBUSINTERRUPT0" pos="26" type="boolean"/>
+ <bitfield name="DEBUGBUSINTERRUPT1" pos="27" type="boolean"/>
+ <bitfield name="TSBWRITEERROR" pos="28" type="boolean"/>
+ <bitfield name="ISDBCPUIRQ" pos="30" type="boolean"/>
+ <bitfield name="ISDBUNDERDEBUG" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x003a" name="RBBM_INT_2_MASK"/>
+ <reg32 offset="0x0042" name="RBBM_SP_HYST_CNT"/>
+ <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
+ <reg32 offset="0x0044" name="RBBM_RAC_THRESHOLD_CNT"/>
+ <reg32 offset="0x00ae" name="RBBM_CLOCK_CNTL"/>
+ <reg32 offset="0x00b0" name="RBBM_CLOCK_CNTL_SP0"/>
+ <reg32 offset="0x00b4" name="RBBM_CLOCK_CNTL2_SP0"/>
+ <reg32 offset="0x00b8" name="RBBM_CLOCK_DELAY_SP0"/>
+ <reg32 offset="0x00bc" name="RBBM_CLOCK_HYST_SP0"/>
+ <reg32 offset="0x00c0" name="RBBM_CLOCK_CNTL_TP0"/>
+ <reg32 offset="0x00c4" name="RBBM_CLOCK_CNTL2_TP0"/>
+ <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL3_TP0"/>
+ <reg32 offset="0x00cc" name="RBBM_CLOCK_CNTL4_TP0"/>
+ <reg32 offset="0x00d0" name="RBBM_CLOCK_DELAY_TP0"/>
+ <reg32 offset="0x00d4" name="RBBM_CLOCK_DELAY2_TP0"/>
+ <reg32 offset="0x00d8" name="RBBM_CLOCK_DELAY3_TP0"/>
+ <reg32 offset="0x00dc" name="RBBM_CLOCK_DELAY4_TP0"/>
+ <reg32 offset="0x00e0" name="RBBM_CLOCK_HYST_TP0"/>
+ <reg32 offset="0x00e4" name="RBBM_CLOCK_HYST2_TP0"/>
+ <reg32 offset="0x00e8" name="RBBM_CLOCK_HYST3_TP0"/>
+ <reg32 offset="0x00ec" name="RBBM_CLOCK_HYST4_TP0"/>
+ <reg32 offset="0x00f0" name="RBBM_CLOCK_CNTL_RB0"/>
+ <reg32 offset="0x00f4" name="RBBM_CLOCK_CNTL2_RB0"/>
+ <reg32 offset="0x00f8" name="RBBM_CLOCK_CNTL_CCU0"/>
+ <reg32 offset="0x0100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
+ <reg32 offset="0x0104" name="RBBM_CLOCK_CNTL_RAC"/>
+ <reg32 offset="0x0105" name="RBBM_CLOCK_CNTL2_RAC"/>
+ <reg32 offset="0x0106" name="RBBM_CLOCK_DELAY_RAC"/>
+ <reg32 offset="0x0107" name="RBBM_CLOCK_HYST_RAC"/>
+ <reg32 offset="0x0108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
+ <reg32 offset="0x010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
+ <reg32 offset="0x010b" name="RBBM_CLOCK_CNTL_UCHE"/>
+ <reg32 offset="0x010f" name="RBBM_CLOCK_DELAY_UCHE"/>
+ <reg32 offset="0x0110" name="RBBM_CLOCK_HYST_UCHE"/>
+ <reg32 offset="0x0111" name="RBBM_CLOCK_MODE_VFD"/>
+ <reg32 offset="0x0112" name="RBBM_CLOCK_DELAY_VFD"/>
+ <reg32 offset="0x0113" name="RBBM_CLOCK_HYST_VFD"/>
+ <reg32 offset="0x0114" name="RBBM_CLOCK_MODE_GPC"/>
+ <reg32 offset="0x0115" name="RBBM_CLOCK_DELAY_GPC"/>
+ <reg32 offset="0x0116" name="RBBM_CLOCK_HYST_GPC"/>
+ <reg32 offset="0x0117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
+ <reg32 offset="0x0118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
+ <reg32 offset="0x0119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
+ <reg32 offset="0x011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
+ <reg32 offset="0x011b" name="RBBM_CLOCK_MODE_HLSQ"/>
+ <reg32 offset="0x011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
+ <reg32 offset="0x011d" name="RBBM_CLOCK_HYST_HLSQ"/>
+ <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
+ <reg32 offset="0x0210" name="RBBM_STATUS">
+ <bitfield name="CPAHBBUSYCXMASTER" pos="0" type="boolean"/>
+ <bitfield name="CPAHBBUSYCPMASTER" pos="1" type="boolean"/>
+ <bitfield name="CPBUSY" pos="2" type="boolean"/>
+ <bitfield name="GFXDBGCBUSY" pos="3" type="boolean"/>
+ <bitfield name="VBIFGXFPARTBUSY" pos="4" type="boolean"/>
+ <bitfield name="TSEBUSY" pos="5" type="boolean"/>
+ <bitfield name="RASBUSY" pos="6" type="boolean"/>
+ <bitfield name="RBBUSY" pos="7" type="boolean"/>
+ <bitfield name="CCUBUSY" pos="8" type="boolean"/>
+ <bitfield name="A2DBUSY" pos="9" type="boolean"/>
+ <bitfield name="LRZBUSY" pos="10" type="boolean"/>
+ <bitfield name="COMDCOMBUSY" pos="11" type="boolean"/>
+ <bitfield name="PCDCALLBUSY" pos="12" type="boolean"/>
+ <bitfield name="PCVSDBUSY" pos="13" type="boolean"/>
+ <bitfield name="TESSBUSY" pos="14" type="boolean"/>
+ <bitfield name="VFDBUSY" pos="15" type="boolean"/>
+ <bitfield name="VPCBUSY" pos="16" type="boolean"/>
+ <bitfield name="UCHEBUSY" pos="17" type="boolean"/>
+ <bitfield name="SPBUSY" pos="18" type="boolean"/>
+ <bitfield name="TPL1BUSY" pos="19" type="boolean"/>
+ <bitfield name="VSCBUSY" pos="20" type="boolean"/>
+ <bitfield name="HLSQBUSY" pos="21" type="boolean"/>
+ <bitfield name="GPUBUSYIGNAHBCP" pos="22" type="boolean"/>
+ <bitfield name="GPUBUSYIGNAHB" pos="23" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0213" name="RBBM_STATUS3"/>
+ <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP"/>
+ <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ"/>
+ <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS"/>
+ <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS"/>
+ <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD"/>
+ <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC"/>
+ <reg64 offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14"/>
+ <reg64 offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4"/>
+ <reg64 offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8"/>
+ <reg64 offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8"/>
+ <reg64 offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6"/>
+ <reg64 offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6"/>
+ <reg64 offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5"/>
+ <reg64 offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4"/>
+ <reg64 offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4"/>
+ <reg64 offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12"/>
+ <reg64 offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12"/>
+ <reg64 offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24"/>
+ <reg64 offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8"/>
+ <reg64 offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2"/>
+ <reg64 offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4"/>
+ <reg64 offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4"/>
+ <reg64 offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4"/>
+ <reg64 offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6"/>
+ <reg64 offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7"/>
+ <reg64 offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12"/>
+ <reg64 offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6"/>
+ <reg64 offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2"/>
+ <reg64 offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8"/>
+ <reg64 offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8"/>
+ <reg64 offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6"/>
+ <reg64 offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4"/>
+ <reg64 offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4"/>
+ <reg64 offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4"/>
+ <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
+ <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
+ <reg32 offset="0x050b" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
+ <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
+ <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/>
+ <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS"/>
+ <reg64 offset="0x0800" name="CP_RB_BASE"/>
+ <reg32 offset="0x0802" name="CP_RB_CNTL"/>
+ <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
+ <reg32 offset="0x0806" name="CP_RB_RPTR"/>
+ <reg32 offset="0x0807" name="CP_RB_WPTR"/>
+ <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
+ <reg32 offset="0x0812" name="CP_CP2GMU_STATUS"/>
+ <reg32 offset="0x0821" name="CP_HW_FAULT"/>
+ <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS">
+ <bitfield name="OPCODEERROR" pos="0" type="boolean"/>
+ <bitfield name="UCODEERROR" pos="1" type="boolean"/>
+ <bitfield name="CPHWFAULT" pos="2" type="boolean"/>
+ <bitfield name="REGISTERPROTECTION" pos="4" type="boolean"/>
+ <bitfield name="VSDPARITYERROR" pos="6" type="boolean"/>
+ <bitfield name="ILLEGALINSTRUCTION" pos="7" type="boolean"/>
+ <bitfield name="OPCODEERRORLPAC" pos="8" type="boolean"/>
+ <bitfield name="UCODEERRORLPAC" pos="9" type="boolean"/>
+ <bitfield name="CPHWFAULTLPAC" pos="10" type="boolean"/>
+ <bitfield name="REGISTERPROTECTIONLPAC" pos="11" type="boolean"/>
+ <bitfield name="ILLEGALINSTRUCTIONLPAC" pos="12" type="boolean"/>
+ <bitfield name="OPCODEERRORBV" pos="13" type="boolean"/>
+ <bitfield name="UCODEERRORBV" pos="14" type="boolean"/>
+ <bitfield name="CPHWFAULTBV" pos="15" type="boolean"/>
+ <bitfield name="REGISTERPROTECTIONBV" pos="16" type="boolean"/>
+ <bitfield name="ILLEGALINSTRUCTIONBV" pos="17" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
+ <reg32 offset="0x0825" name="CP_STATUS_1"/>
+ <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
+ <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
+ <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
+ <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
+ <reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
+ <reg32 offset="0x084f" name="CP_PROTECT_CNTL"/>
+ <reg32 offset="0x0850" name="CP_PROTECT_REG" stride="1" length="48"/>
+ <reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL"/>
+ <reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
+ <reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
+ <reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
+ <reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
+ <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS"/>
+ <reg32 offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
+ <reg32 offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7"/>
+ <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>
+ <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
+ <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
+ <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
+ <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
+ <reg32 offset="0x090a" name="CP_DRAW_STATE_ADDR"/>
+ <reg32 offset="0x090b" name="CP_DRAW_STATE_DATA"/>
+ <reg32 offset="0x090c" name="CP_ROQ_DBG_ADDR"/>
+ <reg32 offset="0x090d" name="CP_ROQ_DBG_DATA"/>
+ <reg32 offset="0x090e" name="CP_MEM_POOL_DBG_ADDR"/>
+ <reg32 offset="0x090f" name="CP_MEM_POOL_DBG_DATA"/>
+ <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
+ <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
+ <reg64 offset="0x0928" name="CP_IB1_BASE"/>
+ <reg32 offset="0x092a" name="CP_IB1_REM_SIZE"/>
+ <reg64 offset="0x092b" name="CP_IB2_BASE"/>
+ <reg32 offset="0x092d" name="CP_IB2_REM_SIZE"/>
+ <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
+ <reg32 offset="0x098d" name="CP_AHB_CNTL"/>
+ <reg32 offset="0x0a00" name="CP_APERTURE_CNTL_HOST"/>
+ <reg32 offset="0x0a03" name="CP_APERTURE_CNTL_CD"/>
+ <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS"/>
+ <reg32 offset="0x0a64" name="CP_BV_HW_FAULT"/>
+ <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR"/>
+ <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA"/>
+ <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR"/>
+ <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA"/>
+ <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR"/>
+ <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA"/>
+ <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR"/>
+ <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA"/>
+ <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR"/>
+ <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA"/>
+ <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR"/>
+ <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR"/>
+ <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA"/>
+ <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL"/>
+ <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG"/>
+ <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR"/>
+ <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA"/>
+ <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR"/>
+ <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR"/>
+ <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA"/>
+ <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR"/>
+ <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA"/>
+ <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL"/>
+ <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA"/>
+ <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA"/>
+ <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR"/>
+ <reg32 offset="0x0cd8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
+ <reg32 offset="0x0e01" name="UCHE_MODE_CNTL"/>
+ <reg64 offset="0x0e07" name="UCHE_WRITE_THRU_BASE"/>
+ <reg64 offset="0x0e09" name="UCHE_TRAP_BASE"/>
+ <reg64 offset="0x0e0b" name="UCHE_GMEM_RANGE_MIN"/>
+ <reg64 offset="0x0e0d" name="UCHE_GMEM_RANGE_MAX"/>
+ <reg32 offset="0x0e17" name="UCHE_CACHE_WAYS"/>
+ <reg32 offset="0x0e19" name="UCHE_CLIENT_PF"/>
+ <reg32 offset="0x0e1c" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
+ <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
+ <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
+ <reg32 offset="0x1140" name="PDC_GPU_ENABLE_PDC"/>
+ <reg32 offset="0x1148" name="PDC_GPU_SEQ_START_ADDR"/>
+ <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
+ <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
+ <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
+ <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/>
+ <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
+ <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/>
+ <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
+ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
+ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
+ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
+ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
+ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
+ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
+ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
+ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
+ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
+ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
+ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
+ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
+ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
+ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
+ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
+ <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
+ <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
+ <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
+ <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
+ <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
+ <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
+ <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
+ <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
+ <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
+ <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
+ <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
+ <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
+ <reg32 offset="0x3c45" name="GBIF_HALT"/>
+ <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
+ <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
+ <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
+ <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
+ <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
+ <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
+ <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
+ <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
+ <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
+ <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
+ <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
+ <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
+ <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
+ <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
+ <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
+ <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
+ <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
+ <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
+ <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
+ <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL"/>
+ <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
+ <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
+ <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
+ <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"/>
+ <reg32 offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
+ <reg32 offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
+ <reg32 offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
+ <reg32 offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6"/>
+ <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
+ <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
+ <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
+ <reg32 offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12"/>
+ <reg32 offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16"/>
+ <reg32 offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16"/>
+ <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"/>
+ <reg32 offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
+ <reg32 offset="0xae6d" name="SP_READ_SEL"/>
+ <reg32 offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36"/>
+ <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"/>
+ <reg32 offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18"/>
+ <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE"/>
+ <reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/>
+ <reg64 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
+ <reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
+ <reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/>
+ <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS"/>
+</domain>
+
+</database>
diff --git a/src/freedreno/registers/adreno/adreno_common.xml b/src/freedreno/registers/adreno/adreno_common.xml
index d9fc4ab3f41..212839eba85 100644
--- a/src/freedreno/registers/adreno/adreno_common.xml
+++ b/src/freedreno/registers/adreno/adreno_common.xml
@@ -9,6 +9,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="A4XX"/>
<value name="A5XX"/>
<value name="A6XX"/>
+ <value name="A7XX"/>
</enum>
<enum name="adreno_pa_su_sc_draw">
diff --git a/src/freedreno/registers/adreno/adreno_pm4.xml b/src/freedreno/registers/adreno/adreno_pm4.xml
index a29094e6c36..1d901f648ef 100644
--- a/src/freedreno/registers/adreno/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno/adreno_pm4.xml
@@ -65,6 +65,22 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<!-- a6xx events -->
<value name="CACHE_INVALIDATE" value="49" varset="chip" variants="A6XX"/>
+
+ <!-- note, some of these are the same as a6xx, just named differently -->
+ <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/>
+ <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/>
+ <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/>
+ <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/>
+ <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/>
+ <value name="CCU_RESOLVE" value="30" variants="A7XX"/>
+ <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
+ <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/>
+ <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/>
+ <value name="CACHE_RESET" value="48" variants="A7XX"/>
+ <value name="CACHE_CLEAN" value="49" variants="A7XX"/>
+ <!-- TODO: deal with name conflicts with other gens -->
+ <value name="CACHE_FLUSH7" value="50" variants="A7XX"/>
+ <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/>
</enum>
<enum name="pc_di_primtype">
@@ -504,6 +520,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
</doc>
<value name="CP_START_BIN" value="0x50" varset="chip" variants="A6XX"/>
<value name="CP_END_BIN" value="0x51" varset="chip" variants="A6XX"/>
+
+ <value name="CP_WAIT_TIMESTAMP" value="0x14" varset="chip" variants="A7XX-"/>
+ <value name="CP_THREAD_CONTROL" value="0x17" varset="chip" variants="A7XX-"/>
</enum>
@@ -1832,5 +1851,18 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</reg32>
</domain>
+<domain name="CP_THREAD_CONTROL" width="32">
+ <enum name="cp_thread">
+ <value name="CP_SET_THREAD_BR" value="1"/>
+ <value name="CP_SET_THREAD_BV" value="2"/>
+ <value name="CP_SET_THREAD_BOTH" value="3"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield low="0" high="1" name="THREAD" type="cp_thread"/>
+ <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/>
+ <bitfield pos="31" name="SYNC_THREADS" type="boolean"/>
+ </reg32>
+</domain>
+
</database>
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