Mesa (main): pan/bi: Implement f2f16{_rtz, _rtne}
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Fri Jul 8 01:13:50 UTC 2022
Module: Mesa
Branch: main
Commit: 5aa740bc8e67b5a6f7d1ad6bdb22f22ca5cb2c57
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5aa740bc8e67b5a6f7d1ad6bdb22f22ca5cb2c57
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Mon Jun 27 15:46:15 2022 -0400
pan/bi: Implement f2f16{_rtz, _rtne}
Float conversions with explicit rounding modes are required for OpenCL,
as well as for Vulkan with the VK_KHR_16bit_storage extension (mandatory
in Vulkan 1.1). Since the hardware conversion instructions allow
configuring the round mode, this is easy to support :-)
Fixes test_half.vstore_half_rtz.
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17262>
---
src/panfrost/bifrost/bifrost_compile.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/panfrost/bifrost/bifrost_compile.c b/src/panfrost/bifrost/bifrost_compile.c
index b375d924099..e6c97f3f369 100644
--- a/src/panfrost/bifrost/bifrost_compile.c
+++ b/src/panfrost/bifrost/bifrost_compile.c
@@ -2401,14 +2401,28 @@ bi_emit_alu(bi_builder *b, nir_alu_instr *instr)
}
case nir_op_f2f16:
+ case nir_op_f2f16_rtz:
+ case nir_op_f2f16_rtne: {
assert(src_sz == 32);
bi_index idx = bi_src_index(&instr->src[0].src);
bi_index s0 = bi_extract(b, idx, instr->src[0].swizzle[0]);
bi_index s1 = comps > 1 ?
bi_extract(b, idx, instr->src[0].swizzle[1]) : s0;
- bi_v2f32_to_v2f16_to(b, dst, s0, s1);
+ bi_instr *I = bi_v2f32_to_v2f16_to(b, dst, s0, s1);
+
+ /* Override rounding if explicitly requested. Otherwise, the
+ * default rounding mode is selected by the builder. Depending
+ * on the float controls required by the shader, the default
+ * mode may not be nearest-even.
+ */
+ if (instr->op == nir_op_f2f16_rtz)
+ I->round = BI_ROUND_RTZ;
+ else if (instr->op == nir_op_f2f16_rtne)
+ I->round = BI_ROUND_NONE; /* Nearest even */
+
return;
+ }
/* Vectorized downcasts */
case nir_op_u2u16:
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