Mesa (main): anv: ensure tile flush before streamout writes

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Module: Mesa
Branch: main
Commit: 2cac3b38172980ea51ba0ea2bbb6350d057972b0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cac3b38172980ea51ba0ea2bbb6350d057972b0

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Wed Jul 13 03:35:06 2022 +0300

anv: ensure tile flush before streamout writes

Streamout is not L3 coherent so previous writes to the same address
might be pending and overwrite the SO writes later when they get
flushed from L3, even though the SO write happened later in the batch.

v2: Use the right flag (not COUNTER)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6680
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17503>

---

 src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt | 2 --
 src/intel/vulkan/anv_private.h                     | 8 ++++++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt b/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt
index f78ed045674..e69de29bb2d 100644
--- a/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt
+++ b/src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt
@@ -1,2 +0,0 @@
-# 6205
-KHR-GL46.tessellation_shader.single.xfb_captures_data_from_correct_stage,Fail
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 300fa951c68..3b5eb704340 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2567,6 +2567,14 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_device *device,
           */
          pipe_bits |= ANV_PIPE_FLUSH_BITS;
          break;
+      case VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
+         /* We're transitioning a buffer to be written by the streamout fixed
+          * function. This one is apparently not L3 coherent, so we need a
+          * tile cache flush to make sure any previous write is not going to
+          * create WaW hazards.
+          */
+         pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
+         break;
       default:
          break; /* Nothing to do */
       }