Mesa (main): radv: Add flushing for DGC.

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Module: Mesa
Branch: main
Commit: 848d3fdeb6d28f809832e9287e1413e535724d2c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=848d3fdeb6d28f809832e9287e1413e535724d2c

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Jun 28 00:14:49 2022 +0200

radv: Add flushing for DGC.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17269>

---

 src/amd/vulkan/radv_cmd_buffer.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 29cc79aae0e..94d1e55494d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4175,6 +4175,15 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 dst_fla
          /* SMEM loads are used to read compute dispatch size in shaders */
          if (!cmd_buffer->device->load_grid_size_from_user_sgpr)
             flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
+
+         /* Ensure the DGC meta shader can read the commands. */
+         if (cmd_buffer->device->uses_device_generated_commands) {
+            flush_bits |= RADV_CMD_FLAG_INV_SCACHE | RADV_CMD_FLAG_INV_VCACHE;
+
+            if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX9)
+               flush_bits |= RADV_CMD_FLAG_INV_L2;
+         }
+
          break;
       case VK_ACCESS_2_INDEX_READ_BIT:
       case VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT: