Mesa (main): radv: declare a new user SGPR arg in FS for the epilog PC

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Module: Mesa
Branch: main
Commit: a38db1a94e1e524bede800bad03621e472a0bffd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a38db1a94e1e524bede800bad03621e472a0bffd

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Fri Jun 17 16:22:18 2022 +0200

radv: declare a new user SGPR arg in FS for the epilog PC

The main FS would have to jump to the PC of the PS epilog. Given that
shaders are allocated in the 32-bit addr space, one user SGPR is fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17485>

---

 src/amd/vulkan/radv_shader.h      | 1 +
 src/amd/vulkan/radv_shader_args.c | 9 +++++++++
 src/amd/vulkan/radv_shader_args.h | 3 +++
 3 files changed, 13 insertions(+)

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 96ff3f23d20..4a03789fc8c 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -156,6 +156,7 @@ enum radv_ud_index {
    AC_UD_VS_BASE_VERTEX_START_INSTANCE,
    AC_UD_VS_PROLOG_INPUTS,
    AC_UD_VS_MAX_UD,
+   AC_UD_PS_EPILOG_PC,
    AC_UD_PS_MAX_UD,
    AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
    AC_UD_CS_SBT_DESCRIPTORS,
diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c
index e63013b9be9..05765531584 100644
--- a/src/amd/vulkan/radv_shader_args.c
+++ b/src/amd/vulkan/radv_shader_args.c
@@ -183,6 +183,9 @@ allocate_user_sgprs(enum amd_gfx_level gfx_level, const struct radv_shader_info
          user_sgpr_count += 4; /* ring_entry, 2x ib_addr, ib_stride */
       break;
    case MESA_SHADER_FRAGMENT:
+      /* epilog continue PC */
+      if (info->ps.has_epilog)
+         user_sgpr_count += 1;
       break;
    case MESA_SHADER_VERTEX:
       if (!args->is_gs_copy_shader)
@@ -785,6 +788,10 @@ radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipelin
    case MESA_SHADER_FRAGMENT:
       declare_global_input_sgprs(info, &user_sgpr_info, args);
 
+      if (info->ps.has_epilog) {
+         ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ps_epilog_pc);
+      }
+
       ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.prim_mask);
       if (args->explicit_scratch_args && gfx_level < GFX11) {
          ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.scratch_offset);
@@ -876,6 +883,8 @@ radv_declare_shader_args(enum amd_gfx_level gfx_level, const struct radv_pipelin
       }
       break;
    case MESA_SHADER_FRAGMENT:
+      if (args->ps_epilog_pc.used)
+         set_loc_shader(args, AC_UD_PS_EPILOG_PC, &user_sgpr_idx, 1);
       break;
    default:
       unreachable("Shader stage not implemented");
diff --git a/src/amd/vulkan/radv_shader_args.h b/src/amd/vulkan/radv_shader_args.h
index 0d373719d71..ee6540ed3de 100644
--- a/src/amd/vulkan/radv_shader_args.h
+++ b/src/amd/vulkan/radv_shader_args.h
@@ -56,6 +56,9 @@ struct radv_shader_args {
    struct ac_arg task_ib_addr;
    struct ac_arg task_ib_stride;
 
+   /* Fragment shaders */
+   struct ac_arg ps_epilog_pc;
+
    struct ac_arg prolog_inputs;
    struct ac_arg vs_inputs[MAX_VERTEX_ATTRIBS];