Mesa (main): lavapipe: set image access on pipeline bind, not descriptor bind

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Module: Mesa
Branch: main
Commit: 725cdfb0ad627383506cd3d7f014b93d3998a110
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=725cdfb0ad627383506cd3d7f014b93d3998a110

Author: Mike Blumenkrantz <michael.blumenkrantz at gmail.com>
Date:   Mon Jul 25 11:32:02 2022 -0400

lavapipe: set image access on pipeline bind, not descriptor bind

this is where the access originates, so set it here

Reviewed-by: Dave Airlie <airlied at redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17739>

---

 src/gallium/frontends/lavapipe/lvp_execute.c | 37 +++++++++++++++++-----------
 1 file changed, 23 insertions(+), 14 deletions(-)

diff --git a/src/gallium/frontends/lavapipe/lvp_execute.c b/src/gallium/frontends/lavapipe/lvp_execute.c
index 3bad295199d..dee4752a8af 100644
--- a/src/gallium/frontends/lavapipe/lvp_execute.c
+++ b/src/gallium/frontends/lavapipe/lvp_execute.c
@@ -1103,14 +1103,35 @@ static void handle_graphics_pipeline(struct vk_cmd_queue_entry *cmd,
    }
 }
 
+static void
+handle_pipeline_access(struct rendering_state *state, enum pipe_shader_type pstage)
+{
+   for (unsigned i = 0; i < PIPE_MAX_SHADER_IMAGES; i++) {
+      state->iv[pstage][i].access = 0;
+      state->iv[pstage][i].shader_access = 0;
+   }
+   u_foreach_bit(idx, state->access[pstage].images_read) {
+      state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_READ;
+      state->iv[pstage][idx].shader_access |= PIPE_IMAGE_ACCESS_READ;
+   }
+   u_foreach_bit(idx, state->access[pstage].images_written) {
+      state->iv[pstage][idx].access |= PIPE_IMAGE_ACCESS_WRITE;
+      state->iv[pstage][idx].shader_access |= PIPE_IMAGE_ACCESS_WRITE;
+   }
+}
+
 static void handle_pipeline(struct vk_cmd_queue_entry *cmd,
                             struct rendering_state *state)
 {
    LVP_FROM_HANDLE(lvp_pipeline, pipeline, cmd->u.bind_pipeline.pipeline);
-   if (pipeline->is_compute_pipeline)
+   if (pipeline->is_compute_pipeline) {
       handle_compute_pipeline(cmd, state);
-   else
+      handle_pipeline_access(state, PIPE_SHADER_COMPUTE);
+   } else {
       handle_graphics_pipeline(cmd, state);
+      for (unsigned i = 0; i < PIPE_SHADER_COMPUTE; i++)
+         handle_pipeline_access(state, i);
+   }
    state->push_size[pipeline->is_compute_pipeline] = pipeline->layout->push_constant_size;
    state->pipeline[pipeline->is_compute_pipeline] = pipeline;
 }
@@ -1355,18 +1376,6 @@ static void fill_image_view_stage(struct rendering_state *state,
       state->iv[p_stage][idx].u.tex.level = 0;
    }
 
-   assert(idx < 32);
-   state->iv[p_stage][idx].access = 0;
-   state->iv[p_stage][idx].shader_access = 0;
-   if (state->access[stage].images_read & BITFIELD_BIT(idx)) {
-      state->iv[p_stage][idx].access |= PIPE_IMAGE_ACCESS_READ;
-      state->iv[p_stage][idx].shader_access |= PIPE_IMAGE_ACCESS_READ;
-   }
-   if (state->access[stage].images_written & BITFIELD_BIT(idx)) {
-      state->iv[p_stage][idx].access |= PIPE_IMAGE_ACCESS_WRITE;
-      state->iv[p_stage][idx].shader_access |= PIPE_IMAGE_ACCESS_WRITE;
-   }
-
    if (state->num_shader_images[p_stage] <= idx)
       state->num_shader_images[p_stage] = idx + 1;