Mesa (main): tu: Fix resolving d32s8 into s8 on fast path

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Module: Mesa
Branch: main
Commit: 19a23534468959251c27b5c8ef53f1596ac9c0ed
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=19a23534468959251c27b5c8ef53f1596ac9c0ed

Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Jul 21 17:25:41 2022 +0200

tu: Fix resolving d32s8 into s8 on fast path

The code assumed that if the source was d32s8 then the destination would
also be d32s8, in particular that depth_base_addr/stencil_base_addr
would also be filled out. Move the destination and source handling into
two different ifs with different conditions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17684>

---

 src/freedreno/ci/freedreno-a618-fails.txt |  6 ------
 src/freedreno/vulkan/tu_clear_blit.c      | 15 +++++++--------
 2 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/src/freedreno/ci/freedreno-a618-fails.txt b/src/freedreno/ci/freedreno-a618-fails.txt
index 86d36560e48..f7a51bc023e 100644
--- a/src/freedreno/ci/freedreno-a618-fails.txt
+++ b/src/freedreno/ci/freedreno-a618-fails.txt
@@ -2,15 +2,9 @@
 gmem-dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.graphics.writes_two_buffers_geom,Fail
 gmem-dEQP-VK.spirv_assembly.instruction.graphics.variable_pointers.graphics.writes_two_buffers_vert,Fail
 
-# VK-GL-CTS 1.3.2.0 uprev
-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
-gmem-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
-
 # https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/3590
 dEQP-VK.api.info.get_physical_device_properties2.memory_properties,Fail
 
-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d32_sfloat_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
-
 # https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/3759
 # deqp-vk: ../src/freedreno/vulkan/tu_pipeline.c:3894: tu_pipeline_builder_init_graphics: Assertion `subpass->color_count == 0 || !create_info->pColorBlendState || subpass->color_count == create_info->pColorBlendState->attachmentCount' failed
 dEQP-VK.pipeline.monolithic.color_write_enable_maxa.cwe_after_bind.attachments4_more0,Crash
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index 8178cdb8beb..7a374628c1e 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -2958,7 +2958,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
          vk_format_is_depth_or_stencil(attachment->format)));
 
    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4);
-   if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
+   if (iview->image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
       if (!separate_stencil) {
          tu_cs_emit(cs, tu_image_view_depth(iview, RB_BLIT_DST_INFO));
          tu_cs_emit_qw(cs, iview->depth_base_addr);
@@ -2966,16 +2966,10 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
 
          tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
          tu_cs_image_flag_ref(cs, &iview->view, 0);
-
-         tu_cs_emit_regs(cs,
-                        A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
       } else {
          tu_cs_emit(cs, tu_image_view_stencil(iview, RB_BLIT_DST_INFO) & ~A6XX_RB_BLIT_DST_INFO_FLAGS);
          tu_cs_emit_qw(cs, iview->stencil_base_addr);
          tu_cs_emit(cs, iview->stencil_PITCH);
-
-         tu_cs_emit_regs(cs,
-                        A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset_stencil));
       }
    } else {
       tu_cs_emit(cs, iview->view.RB_BLIT_DST_INFO);
@@ -2983,9 +2977,14 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
 
       tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
       tu_cs_image_flag_ref(cs, &iview->view, 0);
+   }
 
+   if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT && separate_stencil) {
+         tu_cs_emit_regs(cs,
+                        A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset_stencil));
+   } else {
       tu_cs_emit_regs(cs,
-                      A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
+                     A6XX_RB_BLIT_BASE_GMEM(attachment->gmem_offset));
    }
 
    tu6_emit_event_write(cmd, cs, BLIT);