Mesa (staging/22.1): iris,anv: correct the max thread number for DG2+

[GitLab Mirror]

Module: Mesa
Branch: staging/22.1
Commit: 4d8ef8b21bb293aa9a476b8ea3cfe3225fa13332
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d8ef8b21bb293aa9a476b8ea3cfe3225fa13332

Author: Chuansheng Liu <chuansheng.liu at intel.com>
Date:   Fri Jun 24 10:19:03 2022 +0800

iris,anv: correct the max thread number for DG2+

Correct the max thread number for DG2+ platforms according
to below bspec.

Ref: Bspec: 47202

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chuansheng Liu <chuansheng.liu at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17506>
(cherry picked from commit 39f8c61f32594c058acf0148b62fb444ea81a043)

---

 .pick_status.json                     | 2 +-
 src/gallium/drivers/iris/iris_state.c | 2 +-
 src/intel/blorp/blorp_genX_exec.h     | 2 +-
 src/intel/vulkan/genX_pipeline.c      | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 47b218c4ce4..6365f114dc9 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -6196,7 +6196,7 @@
         "description": "iris,anv: correct the max thread number for DG2+",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index fec6d07aae6..fb02f5ff8b1 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -7121,7 +7121,7 @@ iris_upload_compute_walker(struct iris_context *ice,
    if (stage_dirty & IRIS_STAGE_DIRTY_CS) {
       iris_emit_cmd(batch, GENX(CFE_STATE), cfe) {
          cfe.MaximumNumberofThreads =
-            devinfo->max_cs_threads * devinfo->subslice_total - 1;
+            devinfo->max_cs_threads * devinfo->subslice_total;
          uint32_t scratch_addr = pin_scratch_space(ice, batch, prog_data,
                                                    MESA_SHADER_COMPUTE);
          cfe.ScratchSpaceBuffer = scratch_addr >> 4;
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index d63bea31f8a..e85e411859b 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -2157,7 +2157,7 @@ blorp_exec_compute(struct blorp_batch *batch, const struct blorp_params *params)
 
    blorp_emit(batch, GENX(CFE_STATE), cfe) {
       cfe.MaximumNumberofThreads =
-         devinfo->max_cs_threads * devinfo->subslice_total - 1;
+         devinfo->max_cs_threads * devinfo->subslice_total;
    }
 
    assert(cs_prog_data->push.per_thread.regs == 0);
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 774b77e3c9b..ac1266c51ff 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -2853,7 +2853,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
 
    anv_batch_emit(&pipeline->base.batch, GENX(CFE_STATE), cfe) {
       cfe.MaximumNumberofThreads =
-         devinfo->max_cs_threads * devinfo->subslice_total - 1;
+         devinfo->max_cs_threads * devinfo->subslice_total;
       cfe.ScratchSpaceBuffer =
          get_scratch_surf(&pipeline->base, MESA_SHADER_COMPUTE, cs_bin);
    }