Mesa (main): aco: Implement uclz.
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Wed Jun 1 17:59:53 UTC 2022
Module: Mesa
Branch: main
Commit: 529ec3d7dc1dd74060bda205743e1e3ae4a88349
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=529ec3d7dc1dd74060bda205743e1e3ae4a88349
Author: Georg Lehmann <dadschoorse at gmail.com>
Date: Fri Nov 19 14:27:06 2021 +0100
aco: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
---
src/amd/compiler/aco_instruction_selection.cpp | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 63ac939e20f..e09c2c281c9 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -1768,6 +1768,19 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
}
break;
}
+ case nir_op_uclz: {
+ Temp src = get_alu_src(ctx, instr->src[0]);
+ if (src.regClass() == s1) {
+ Temp msb_rev = bld.sop1(aco_opcode::s_flbit_i32_b32, bld.def(s1), src);
+ bld.sop2(aco_opcode::s_min_u32, Definition(dst), Operand::c32(32u), msb_rev);
+ } else if (src.regClass() == v1) {
+ Temp msb_rev = bld.vop1(aco_opcode::v_ffbh_u32, bld.def(v1), src);
+ bld.vop2(aco_opcode::v_min_u32, Definition(dst), Operand::c32(32u), msb_rev);
+ } else {
+ isel_err(&instr->instr, "Unimplemented NIR instr bit size");
+ }
+ break;
+ }
case nir_op_bitfield_reverse: {
if (dst.regClass() == s1) {
bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
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