Mesa (main): panfrost: Don't allow vertex shaders to have side effects

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Module: Mesa
Branch: main
Commit: 45dc15d07b2f6deacf71732c6a5bd6086069318b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=45dc15d07b2f6deacf71732c6a5bd6086069318b

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Mon Apr  4 15:58:10 2022 -0400

panfrost: Don't allow vertex shaders to have side effects

In both GL and VK, the driver may choose not to support vertex shaders with side
effects (SSBOs, atomics, images). Supporting this opens a can of worms for IDVS.
Neither freedreno nor the (Vulkan?) DDK advertise support, for this reason.
Apps should not be using this anti-feature anyway.

Stop advertising support.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15720>

---

 src/gallium/drivers/panfrost/pan_screen.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_screen.c b/src/gallium/drivers/panfrost/pan_screen.c
index d6265180906..79a09818cda 100644
--- a/src/gallium/drivers/panfrost/pan_screen.c
+++ b/src/gallium/drivers/panfrost/pan_screen.c
@@ -355,6 +355,16 @@ panfrost_get_shader_param(struct pipe_screen *screen,
                 return 0;
         }
 
+        /* We only allow observable side effects (memory writes) in compute and
+         * fragment shaders. Side effects in the geometry pipeline cause
+         * trouble with IDVS.
+         *
+         * This restriction doesn't apply to Midgard, which does not implement
+         * IDVS and therefore executes vertex shaders exactly once.
+         */
+        bool allow_side_effects = (shader != PIPE_SHADER_VERTEX) ||
+                                  (dev->arch <= 5);
+
         switch (param) {
         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
@@ -442,10 +452,10 @@ panfrost_get_shader_param(struct pipe_screen *screen,
                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 
         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
-                return 16;
+                return allow_side_effects ? 16 : 0;
 
         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
-                return PIPE_MAX_SHADER_IMAGES;
+                return allow_side_effects ? PIPE_MAX_SHADER_IMAGES : 0;
 
         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: